drivers: pinctrl: nrf: Add support for PWM, QDEC, and QSPI peripherals
Add support for configuring pins to be used by the nRF PWM, QDEC, and QSPI peripherals. A new custom property "nordic,invert" is added to the pin configuration group binding to allow configuring PWM channel outputs as inverted. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Carles Cufí
parent
1c20443ce0
commit
fd7633126e
|
|
@ -61,6 +61,18 @@ BUILD_ASSERT(((NRF_DRIVE_S0S1 == NRF_GPIO_PIN_S0S1) &&
|
|||
#define NRF_PSEL_PDM(reg, line) ((NRF_PDM_Type *)reg)->PSEL.line
|
||||
#endif
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwm)
|
||||
#define NRF_PSEL_PWM(reg, line) ((NRF_PWM_Type *)reg)->PSEL.line
|
||||
#endif
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qdec)
|
||||
#define NRF_PSEL_QDEC(reg, line) ((NRF_QDEC_Type *)reg)->PSEL.line
|
||||
#endif
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qspi)
|
||||
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Configure pin settings.
|
||||
*
|
||||
|
|
@ -218,6 +230,81 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
|
|||
NRF_GPIO_PIN_INPUT_CONNECT);
|
||||
break;
|
||||
#endif /* defined(NRF_PSEL_PDM) */
|
||||
#if defined(NRF_PSEL_PWM)
|
||||
case NRF_FUN_PWM_OUT0:
|
||||
NRF_PSEL_PWM(reg, OUT[0]) = NRF_GET_PIN(pins[i]);
|
||||
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
|
||||
NRF_GET_INVERT(pins[i]));
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
case NRF_FUN_PWM_OUT1:
|
||||
NRF_PSEL_PWM(reg, OUT[1]) = NRF_GET_PIN(pins[i]);
|
||||
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
|
||||
NRF_GET_INVERT(pins[i]));
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
case NRF_FUN_PWM_OUT2:
|
||||
NRF_PSEL_PWM(reg, OUT[2]) = NRF_GET_PIN(pins[i]);
|
||||
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
|
||||
NRF_GET_INVERT(pins[i]));
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
case NRF_FUN_PWM_OUT3:
|
||||
NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
|
||||
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
|
||||
NRF_GET_INVERT(pins[i]));
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
#endif /* defined(NRF_PSEL_PWM) */
|
||||
#if defined(NRF_PSEL_QDEC)
|
||||
case NRF_FUN_QDEC_A:
|
||||
NRF_PSEL_QDEC(reg, A) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_CONNECT);
|
||||
break;
|
||||
case NRF_FUN_QDEC_B:
|
||||
NRF_PSEL_QDEC(reg, B) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_CONNECT);
|
||||
case NRF_FUN_QDEC_LED:
|
||||
NRF_PSEL_QDEC(reg, LED) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_CONNECT);
|
||||
break;
|
||||
#endif /* defined(NRF_PSEL_QDEC) */
|
||||
#if defined(NRF_PSEL_QSPI)
|
||||
case NRF_FUN_QSPI_SCK:
|
||||
NRF_PSEL_QSPI(reg, SCK) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
case NRF_FUN_QSPI_CSN:
|
||||
NRF_PSEL_QSPI(reg, CSN) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
case NRF_FUN_QSPI_IO0:
|
||||
NRF_PSEL_QSPI(reg, IO0) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
case NRF_FUN_QSPI_IO1:
|
||||
NRF_PSEL_QSPI(reg, IO1) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
case NRF_FUN_QSPI_IO2:
|
||||
NRF_PSEL_QSPI(reg, IO2) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
case NRF_FUN_QSPI_IO3:
|
||||
NRF_PSEL_QSPI(reg, IO3) = NRF_GET_PIN(pins[i]);
|
||||
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT);
|
||||
break;
|
||||
#endif /* defined(NRF_PSEL_QSPI) */
|
||||
default:
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -108,3 +108,9 @@ child-binding:
|
|||
nrf-pinctrl.h. Note that extra modes may not be available on certain
|
||||
devices. Defaults to standard mode for 0 and 1 (NRF_DRIVE_S0S1), the
|
||||
SoC default.
|
||||
|
||||
nordic,invert:
|
||||
type: boolean
|
||||
description: |
|
||||
Invert pin polarity (set the active state to low).
|
||||
Only valid for PWM channel output pins.
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@
|
|||
* organized as follows:
|
||||
*
|
||||
* - 31..16: Pin function.
|
||||
* - 15..13: Reserved.
|
||||
* - 15..14: Reserved.
|
||||
* - 13: Pin inversion mode.
|
||||
* - 12: Pin low power mode.
|
||||
* - 11..8: Pin output drive configuration.
|
||||
* - 7..6: Pin pull configuration.
|
||||
|
|
@ -27,6 +28,10 @@
|
|||
#define NRF_FUN_POS 16U
|
||||
/** Mask for the function field. */
|
||||
#define NRF_FUN_MSK 0xFFFFU
|
||||
/** Position of the invert field. */
|
||||
#define NRF_INVERT_POS 13U
|
||||
/** Mask for the invert field. */
|
||||
#define NRF_INVERT_MSK 0x1U
|
||||
/** Position of the low power field. */
|
||||
#define NRF_LP_POS 12U
|
||||
/** Mask for the low power field. */
|
||||
|
|
@ -95,6 +100,32 @@
|
|||
#define NRF_FUN_PDM_CLK 20U
|
||||
/** PDM DIN */
|
||||
#define NRF_FUN_PDM_DIN 21U
|
||||
/** PWM OUT0 */
|
||||
#define NRF_FUN_PWM_OUT0 22U
|
||||
/** PWM OUT1 */
|
||||
#define NRF_FUN_PWM_OUT1 23U
|
||||
/** PWM OUT2 */
|
||||
#define NRF_FUN_PWM_OUT2 24U
|
||||
/** PWM OUT3 */
|
||||
#define NRF_FUN_PWM_OUT3 25U
|
||||
/** QDEC A */
|
||||
#define NRF_FUN_QDEC_A 26U
|
||||
/** QDEC B */
|
||||
#define NRF_FUN_QDEC_B 27U
|
||||
/** QDEC LED */
|
||||
#define NRF_FUN_QDEC_LED 28U
|
||||
/** QSPI SCK */
|
||||
#define NRF_FUN_QSPI_SCK 29U
|
||||
/** QSPI CSN */
|
||||
#define NRF_FUN_QSPI_CSN 30U
|
||||
/** QSPI IO0 */
|
||||
#define NRF_FUN_QSPI_IO0 31U
|
||||
/** QSPI IO1 */
|
||||
#define NRF_FUN_QSPI_IO1 32U
|
||||
/** QSPI IO2 */
|
||||
#define NRF_FUN_QSPI_IO2 33U
|
||||
/** QSPI IO3 */
|
||||
#define NRF_FUN_QSPI_IO3 34U
|
||||
|
||||
/** @} */
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,8 @@ typedef uint32_t pinctrl_soc_pin_t;
|
|||
((NRF_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << NRF_PULL_POS) |\
|
||||
((NRF_PULL_UP * DT_PROP(node_id, bias_pull_up)) << NRF_PULL_POS) | \
|
||||
(DT_PROP(node_id, drive_mode) << NRF_DRIVE_POS) | \
|
||||
((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) \
|
||||
((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) |\
|
||||
(DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) \
|
||||
),
|
||||
|
||||
/**
|
||||
|
|
@ -58,6 +59,13 @@ typedef uint32_t pinctrl_soc_pin_t;
|
|||
*/
|
||||
#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin inversion flag.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_INVERT(pincfg) (((pincfg) >> NRF_INVERT_POS) & NRF_INVERT_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin low power flag.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in a new issue