arm: Add support for TI's CC2650 SoC.
Add support in arch/arm/soc/ti_simplelink, along with support for CC32xx SoC. Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
This commit is contained in:
Geoffrey Le Gourriérec
Anas Nashif
parent
4c24b1d857
commit
fdf1785775
17
arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series
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17
arch/arm/soc/ti_simplelink/cc2650/Kconfig.defconfig.series
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# SPDX-License-Identifier: Apache-2.0
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#
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# Kconfig.defconfig.series - TI SimpleLink CC2650
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#
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if SOC_SERIES_CC2650
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config SOC_SERIES
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default cc2650
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 48000000
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config NUM_IRQS
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default 34
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endif # SOC_SERIES_CC2650
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13
arch/arm/soc/ti_simplelink/cc2650/Kconfig.series
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arch/arm/soc/ti_simplelink/cc2650/Kconfig.series
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# SPDX-License-Identifier: Apache-2.0
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#
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# Kconfig.series - TI SimpleLink CC2650
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#
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config SOC_SERIES_CC2650
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bool "TI SimpleLink Family CC2650"
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select CPU_CORTEX_M
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select CPU_CORTEX_M3
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select SOC_FAMILY_TISIMPLELINK
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select CPU_HAS_SYSTICK
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help
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Enable support for TI SimpleLink CC2650.
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21
arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc
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arch/arm/soc/ti_simplelink/cc2650/Kconfig.soc
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# SPDX-License-Identifier: Apache-2.0
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#
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# Kconfig.soc - Texas Instruments CC2650
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#
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choice
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prompt "TI SimpleLink MCU Selection"
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depends on SOC_SERIES_CC2650
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config SOC_CC2650
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bool "CC2650"
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endchoice
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if SOC_SERIES_CC2650
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config TI_CCFG_PRESENT
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bool
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default y
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endif # SOC_SERIES_CC2650
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3
arch/arm/soc/ti_simplelink/cc2650/Makefile
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3
arch/arm/soc/ti_simplelink/cc2650/Makefile
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# SPDX-License-Identifier: Apache-2.0
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obj-y += soc.o
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749
arch/arm/soc/ti_simplelink/cc2650/include/ccfg.h
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749
arch/arm/soc/ti_simplelink/cc2650/include/ccfg.h
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@ -0,0 +1,749 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* CCFG (User configuration area) interface registers and bit offsets
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* for the CC2650 System on Chip.
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*/
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#ifndef _CC2650_CCFG_H_
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#define _CC2650_CCFG_H_
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/* Registers */
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enum CC2650_CCFG_Registers {
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CC2650_CCFG_EXT_LF_CLK = 0xFA8,
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CC2650_CCFG_MODE_CONF_1 = 0xFAC,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS = 0xFB0,
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CC2650_CCFG_MODE_CONF = 0xFB4,
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CC2650_CCFG_VOLT_LOAD_0 = 0xFB8,
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CC2650_CCFG_VOLT_LOAD_1 = 0xFBC,
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CC2650_CCFG_RTC_OFFSET = 0xFC0,
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CC2650_CCFG_FREQ_OFFSET = 0xFC4,
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CC2650_CCFG_IEEE_MAC_0 = 0xFC8,
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CC2650_CCFG_IEEE_MAC_1 = 0xFCC,
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CC2650_CCFG_IEEE_BLE_0 = 0xFD0,
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CC2650_CCFG_IEEE_BLE_1 = 0xFD4,
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CC2650_CCFG_BL_CONFIG = 0xFD8,
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CC2650_CCFG_ERASE_CONF = 0xFDC,
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CC2650_CCFG_CCFG_TI_OPTIONS = 0xFE0,
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CC2650_CCFG_CCFG_TAP_DAP_0 = 0xFE4,
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CC2650_CCFG_CCFG_TAP_DAP_1 = 0xFE8,
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CC2650_CCFG_IMAGE_VALID_CONF = 0xFEC,
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CC2650_CCFG_CCFG_PROT_31_0 = 0xFF0,
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CC2650_CCFG_CCFG_PROT_63_32 = 0xFF4,
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CC2650_CCFG_CCFG_PROT_95_64 = 0xFF8,
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CC2650_CCFG_CCFG_PROT_127_96 = 0xFFC
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};
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/* Register-specific bits */
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/* EXT_LF_CLK */
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enum CC2650_CCFG_EXT_LF_CLK_POS {
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CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_POS = 0,
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CC2650_CCFG_EXT_LF_CLK_DIO_POS = 24
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};
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enum CC2650_CCFG_EXT_LF_CLK_MASK {
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CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK = 0x00FFFFFF,
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CC2650_CCFG_EXT_LF_CLK_DIO_MASK = 0xFF000000
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};
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/* MODE_CONF_1 */
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enum CC2650_CCFG_MODE_CONF_1_POS {
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CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_POS = 0,
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CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_POS = 8,
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CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_POS = 12,
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CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_POS = 16,
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CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_POS = 19,
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CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_POS = 20
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};
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enum CC2650_CCFG_MODE_CONF_1_MASK {
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CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_MASK = 0x000000FF,
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CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_MASK = 0x00000F00,
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CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_MASK = 0x0000F000,
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CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_MASK = 0x00070000,
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CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_MASK = 0x00080000,
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CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_MASK = 0x00F00000
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};
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/* SIZE_AND_DIS_FLAGS */
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enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_POS {
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_POS = 0,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_POS = 1,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_POS = 2,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_POS = 3,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_POS = 4,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_POS = 16
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};
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enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_MASK {
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_MASK =
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0x00000001,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_MASK =
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0x00000002,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_MASK =
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0x00000004,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_MASK =
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0x00000008,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_MASK =
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0x0000FFF0,
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CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_MASK =
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0xFFFF0000
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};
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/* MODE_CONF */
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enum CC2650_CCFG_MODE_CONF_POS {
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CC2650_CCFG_MODE_CONF_VDDR_CAP_POS = 0,
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CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_POS = 8,
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CC2650_CCFG_MODE_CONF_HF_COMP_POS = 16,
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CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_POS = 17,
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CC2650_CCFG_MODE_CONF_XOSC_FREQ_POS = 18,
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CC2650_CCFG_MODE_CONF_RTC_COMP_POS = 20,
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CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_POS = 21,
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CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_POS = 22,
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CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_POS = 24,
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CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_POS = 25,
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CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_POS = 26,
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CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_POS = 27,
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CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_POS = 28
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};
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enum CC2650_CCFG_MODE_CONF_MASK {
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CC2650_CCFG_MODE_CONF_VDDR_CAP_MASK =
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0x000000FF,
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CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_MASK =
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0x0000FF00,
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CC2650_CCFG_MODE_CONF_HF_COMP_MASK =
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0x00010000,
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CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_MASK =
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0x00020000,
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CC2650_CCFG_MODE_CONF_XOSC_FREQ_MASK =
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0x000C0000,
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CC2650_CCFG_MODE_CONF_RTC_COMP_MASK =
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0x00100000,
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CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_MASK =
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0x00200000,
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CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_MASK =
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0x00C00000,
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CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_MASK =
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0x01000000,
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CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_MASK =
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0x02000000,
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CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_MASK =
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0x04000000,
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CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_MASK =
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0x08000000,
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CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_MASK =
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0xF0000000
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};
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/* VOLT_LOAD_0 */
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enum CC2650_CCFG_VOLT_LOAD_0_POS {
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_POS = 0,
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_POS = 8,
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_POS = 16,
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_POS = 24
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};
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enum CC2650_CCFG_VOLT_LOAD_0_MASK {
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_MASK = 0x000000FF,
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_MASK = 0x0000FF00,
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_MASK = 0x00FF0000,
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CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_MASK = 0xFF000000
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};
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/* VOLT_LOAD_1 */
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enum CC2650_CCFG_VOLT_LOAD_1_POS {
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_POS = 0,
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_POS = 8,
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_POS = 16,
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_POS = 24
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};
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enum CC2650_CCFG_VOLT_LOAD_1_MASK {
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_MASK = 0x000000FF,
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_MASK = 0x0000FF00,
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_MASK = 0x00FF0000,
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CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_MASK = 0xFF000000
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};
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/* RTC_OFFSET */
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enum CC2650_CCFG_RTC_OFFSET_POS {
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CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_POS = 0,
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CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_POS = 8,
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CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_POS = 16
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};
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enum CC2650_CCFG_RTC_OFFSET_MASK {
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CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_MASK = 0x000000FF,
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CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_MASK = 0x0000FF00,
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CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_MASK = 0xFFFF0000
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};
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/* FREQ_OFFSET */
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enum CC2650_CCFG_FREQ_OFFSET_POS {
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CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_POS = 0,
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CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_POS = 8,
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CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_POS = 16
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};
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enum CC2650_CCFG_FREQ_OFFSET_MASK {
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CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_MASK = 0x000000FF,
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CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_MASK = 0x0000FF00,
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CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_MASK = 0xFFFF0000
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};
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/* IEEE_MAC_0 */
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enum CC2650_CCFG_IEEE_MAC_0_POS {
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CC2650_CCFG_IEEE_MAC_0_ADDR_POS = 0
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};
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enum CC2650_CCFG_IEEE_MAC_0_MASK {
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CC2650_CCFG_IEEE_MAC_0_ADDR_MASK = 0xFFFFFFFF
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};
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/* IEEE_MAC_1 */
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enum CC2650_CCFG_IEEE_MAC_1_POS {
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CC2650_CCFG_IEEE_MAC_1_ADDR_POS = 0
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};
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enum CC2650_CCFG_IEEE_MAC_1_MASK {
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CC2650_CCFG_IEEE_MAC_1_ADDR_MASK = 0xFFFFFFFF
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};
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/* IEEE_BLE_0 */
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enum CC2650_CCFG_IEEE_BLE_POS {
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CC2650_CCFG_IEEE_BLE_0_ADDR_POS = 0
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};
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enum CC2650_CCFG_IEEE_BLE_MASK {
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CC2650_CCFG_IEEE_BLE_0_ADDR_MASK = 0xFFFFFFFF
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};
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/* IEEE_BLE_1 */
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enum CC2650_CCFG_IEEE_BLE_1_POS {
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CC2650_CCFG_IEEE_BLE_1_ADDR_POS = 0
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};
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enum CC2650_CCFG_IEEE_BLE_1_MASK {
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CC2650_CCFG_IEEE_BLE_1_ADDR_MASK = 0xFFFFFFFF
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};
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/* BL_CONFIG */
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enum CC2650_CCFG_BL_CONFIG_POS {
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CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS = 0,
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CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS = 8,
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CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS = 16,
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CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS = 24
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};
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enum CC2650_CCFG_BL_CONFIG_MASK {
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CC2650_CCFG_BL_CONFIG_BL_ENABLE_MASK = 0x000000FF,
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CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_MASK = 0x0000FF00,
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CC2650_CCFG_BL_CONFIG_BL_LEVEL_MASK = 0x00010000,
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CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_MASK = 0xFF000000
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};
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enum CC2650_CCFG_BL_CONFIG_VALUES {
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CC2650_CCFG_BACKDOOR_ENABLED =
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0xC5 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS,
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CC2650_CCFG_BACKDOOR_DISABLED =
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0x00 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS,
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CC2650_CCFG_BACKDOOR_ACTIVE_HIGH =
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0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS,
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CC2650_CCFG_BACKDOOR_ACTIVE_LOW =
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0x0 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS,
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CC2650_CCFG_BOOTLOADER_ENABLED =
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0xC5 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS,
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CC2650_CCFG_BOOTLOADER_DISABLED =
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0x00 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS
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};
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/* ERASE_CONF */
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enum CC2650_CCFG_ERASE_CONF_POS {
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CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_POS = 0,
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CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_POS = 8
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};
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enum CC2650_CCFG_ERASE_CONF_MASK {
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CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_MASK = 0x00000001,
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CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_MASK = 0x00000100
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};
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/* CCFG_TI_OPTIONS */
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enum CC2650_CCFG_TI_OPTIONS_POS {
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CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS = 0
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};
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enum CC2650_CCFG_TI_OPTIONS_MASK {
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CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_MASK = 0x000000FF
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};
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enum CC2650_CCFG_TI_OPTIONS_VALUES {
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CC2650_CCFG_TI_FA_ENABLED =
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0xC5 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS,
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CC2650_CCFG_TI_FA_DISABLED =
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0x00 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS
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};
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/* CCFG_TAP_DAP_0 */
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enum CC2650_CCFG_TAP_DAP_0_POS {
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CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_POS = 0,
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CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_POS = 8,
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CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_POS = 16
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};
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enum CC2650_CCFG_TAP_DAP_0_MASK {
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CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_MASK =
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0x000000FF,
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CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_MASK =
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0x0000FF00,
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CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_MASK =
|
||||
0x00FF0000
|
||||
};
|
||||
|
||||
/* CCFG_TAP_DAP_1 */
|
||||
enum CC2650_CCFG_CCFG_TAP_DAP_1_POS {
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_POS = 0,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_POS = 8,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_POS = 16
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_TAP_DAP_1_MASK {
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_MASK =
|
||||
0x000000FF,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_MASK =
|
||||
0x0000FF00,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_MASK =
|
||||
0x00FF0000
|
||||
};
|
||||
|
||||
/* IMAGE_VALID_CONF */
|
||||
enum CC2650_CCFG_IMAGE_VALID_CONF_POS {
|
||||
CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IMAGE_VALID_CONF_MASK {
|
||||
CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_MASK = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IMAGE_VALID_CONF_VALUES {
|
||||
CC2650_CCFG_IMAGE_IS_VALID =
|
||||
0x00000000 << CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS
|
||||
};
|
||||
|
||||
/* CCFG_PROT_31_0 */
|
||||
enum CC2650_CCFG_CCFG_PROT_31_0_POS {
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_POS = 0,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_POS = 1,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_POS = 2,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_POS = 3,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_POS = 4,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_POS = 5,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_POS = 6,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_POS = 7,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_POS = 8,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_POS = 9,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_POS = 10,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_POS = 11,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_POS = 12,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_POS = 13,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_POS = 14,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_POS = 15,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_POS = 16,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_POS = 17,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_POS = 18,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_POS = 19,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_POS = 20,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_POS = 21,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_POS = 22,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_POS = 23,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_POS = 24,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_POS = 25,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_POS = 26,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_POS = 27,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_POS = 28,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_POS = 29,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_POS = 30,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_31_0_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
/* CCFG_PROT_63_32 */
|
||||
enum CC2650_CCFG_CCFG_PROT_63_32_POS {
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_POS = 32,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_POS = 33,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_POS = 34,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_POS = 35,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_POS = 36,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_POS = 37,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_POS = 38,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_POS = 39,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_POS = 40,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_POS = 41,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_POS = 42,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_POS = 43,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_POS = 44,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_POS = 45,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_POS = 46,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_POS = 47,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_POS = 48,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_POS = 49,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_POS = 50,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_POS = 51,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_POS = 52,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_POS = 53,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_POS = 54,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_POS = 55,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_POS = 56,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_POS = 57,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_POS = 58,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_POS = 59,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_POS = 60,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_POS = 61,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_POS = 62,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_POS = 63
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_63_32_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
/* CCFG_PROT_95_64 */
|
||||
enum CC2650_CCFG_CCFG_PROT_95_64_POS {
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_POS = 64,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_POS = 65,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_POS = 66,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_POS = 67,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_POS = 68,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_POS = 69,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_POS = 70,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_POS = 71,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_POS = 72,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_POS = 73,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_POS = 74,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_POS = 75,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_POS = 76,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_POS = 77,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_POS = 78,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_POS = 79,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_POS = 80,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_POS = 81,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_POS = 82,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_POS = 83,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_POS = 84,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_POS = 85,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_POS = 86,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_POS = 87,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_POS = 88,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_POS = 89,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_POS = 90,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_POS = 91,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_POS = 92,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_POS = 93,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_POS = 94,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_POS = 95
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_95_64_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
/* CCFG_PROT_127_96 */
|
||||
enum CC2650_CCFG_CCFG_PROT_127_96_POS {
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_POS = 96,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_POS = 97,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_POS = 98,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_POS = 99,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_POS = 100,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_POS = 101,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_POS = 102,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_POS = 103,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_POS = 104,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_POS = 105,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_POS = 106,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_POS = 107,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_POS = 108,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_POS = 109,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_POS = 110,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_POS = 111,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_POS = 112,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_POS = 113,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_POS = 114,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_POS = 115,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_POS = 116,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_POS = 117,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_POS = 118,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_POS = 119,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_POS = 120,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_POS = 121,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_POS = 122,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_POS = 123,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_POS = 124,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_POS = 125,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_POS = 126,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_POS = 127
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_127_96_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
#endif /* _CC2650_CCFG_H_ */
|
||||
658
arch/arm/soc/ti_simplelink/cc2650/include/gpio.h
Normal file
658
arch/arm/soc/ti_simplelink/cc2650/include/gpio.h
Normal file
|
|
@ -0,0 +1,658 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* GPIO registers and bit offsets for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_GPIO_H_
|
||||
#define _CC2650_GPIO_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_GPIO_Registers {
|
||||
CC2650_GPIO_DOUT3_0 = 0x0,
|
||||
CC2650_GPIO_DOUT7_4 = 0x4,
|
||||
CC2650_GPIO_DOUT11_8 = 0x8,
|
||||
CC2650_GPIO_DOUT15_12 = 0xC,
|
||||
CC2650_GPIO_DOUT19_16 = 0x10,
|
||||
CC2650_GPIO_DOUT23_20 = 0x14,
|
||||
CC2650_GPIO_DOUT27_24 = 0x18,
|
||||
CC2650_GPIO_DOUT31_28 = 0x1C,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUT31_0 = 0x80,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUTSET31_0 = 0x90,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUTCLR31_0 = 0XA0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUTTGL31_0 = 0xB0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DIN31_0 = 0xC0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOE31_0 = 0xD0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_EVFLAGS31_0 = 0xE0
|
||||
};
|
||||
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* DOUT3_0 */
|
||||
enum CC2650_GPIO_DOUT3_0_POS {
|
||||
CC2650_GPIO_DOUT3_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUT3_0_DIO1_POS = 8,
|
||||
CC2650_GPIO_DOUT3_0_DIO2_POS = 16,
|
||||
CC2650_GPIO_DOUT3_0_DIO3_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT3_0_MASK {
|
||||
CC2650_GPIO_DOUT3_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT3_0_DIO1_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT3_0_DIO2_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT3_0_DIO3_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT7_4 */
|
||||
enum CC2650_GPIO_DOUT7_4_POS {
|
||||
CC2650_GPIO_DOUT7_4_DIO4_POS = 0,
|
||||
CC2650_GPIO_DOUT7_4_DIO5_POS = 8,
|
||||
CC2650_GPIO_DOUT7_4_DIO6_POS = 16,
|
||||
CC2650_GPIO_DOUT7_4_DIO7_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT7_4_MASK {
|
||||
CC2650_GPIO_DOUT7_4_DIO4_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT7_4_DIO5_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT7_4_DIO6_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT7_4_DIO7_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT11_8 */
|
||||
enum CC2650_GPIO_DOUT11_8_POS {
|
||||
CC2650_GPIO_DOUT11_8_DIO8_POS = 0,
|
||||
CC2650_GPIO_DOUT11_8_DIO9_POS = 8,
|
||||
CC2650_GPIO_DOUT11_8_DIO10_POS = 16,
|
||||
CC2650_GPIO_DOUT11_8_DIO11_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT11_8_MASK {
|
||||
CC2650_GPIO_DOUT11_8_DIO8_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT11_8_DIO9_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT11_8_DIO10_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT11_8_DIO11_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT15_12 */
|
||||
enum CC2650_GPIO_DOUT15_12_POS {
|
||||
CC2650_GPIO_DOUT15_12_DIO12_POS = 0,
|
||||
CC2650_GPIO_DOUT15_12_DIO13_POS = 8,
|
||||
CC2650_GPIO_DOUT15_12_DIO14_POS = 16,
|
||||
CC2650_GPIO_DOUT15_12_DIO15_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT15_12_MASK {
|
||||
CC2650_GPIO_DOUT15_12_DIO12_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT15_12_DIO13_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT15_12_DIO14_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT15_12_DIO15_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT19_16 */
|
||||
enum CC2650_GPIO_DOUT19_16_POS {
|
||||
CC2650_GPIO_DOUT19_16_DIO16_POS = 0,
|
||||
CC2650_GPIO_DOUT19_16_DIO17_POS = 8,
|
||||
CC2650_GPIO_DOUT19_16_DIO18_POS = 16,
|
||||
CC2650_GPIO_DOUT19_16_DIO19_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT19_16_MASK {
|
||||
CC2650_GPIO_DOUT19_16_DIO16_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT19_16_DIO17_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT19_16_DIO18_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT19_16_DIO19_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT23_20 */
|
||||
enum CC2650_GPIO_DOUT23_20_POS {
|
||||
CC2650_GPIO_DOUT23_20_DIO20_POS = 0,
|
||||
CC2650_GPIO_DOUT23_20_DIO21_POS = 8,
|
||||
CC2650_GPIO_DOUT23_20_DIO22_POS = 16,
|
||||
CC2650_GPIO_DOUT23_20_DIO23_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT23_20_MASK {
|
||||
CC2650_GPIO_DOUT23_20_DIO20_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT23_20_DIO21_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT23_20_DIO22_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT23_20_DIO23_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT27_24 */
|
||||
enum CC2650_GPIO_DOUT27_24_POS {
|
||||
CC2650_GPIO_DOUT27_24_DIO24_POS = 0,
|
||||
CC2650_GPIO_DOUT27_24_DIO25_POS = 8,
|
||||
CC2650_GPIO_DOUT27_24_DIO26_POS = 16,
|
||||
CC2650_GPIO_DOUT27_24_DIO27_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT27_24_MASK {
|
||||
CC2650_GPIO_DOUT27_24_DIO24_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT27_24_DIO25_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT27_24_DIO26_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT27_24_DIO27_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT31_28 */
|
||||
enum CC2650_GPIO_DOUT31_28_POS {
|
||||
CC2650_GPIO_DOUT31_28_DIO28_POS = 0,
|
||||
CC2650_GPIO_DOUT31_28_DIO29_POS = 8,
|
||||
CC2650_GPIO_DOUT31_28_DIO30_POS = 16,
|
||||
CC2650_GPIO_DOUT31_28_DIO31_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT31_28_MASK {
|
||||
CC2650_GPIO_DOUT31_28_DIO28 = 0x00000001,
|
||||
CC2650_GPIO_DOUT31_28_DIO29 = 0x00000100,
|
||||
CC2650_GPIO_DOUT31_28_DIO30 = 0x00010000,
|
||||
CC2650_GPIO_DOUT31_28_DIO31 = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT31_0 */
|
||||
enum CC2650_GPIO_DOUT31_0_POS {
|
||||
CC2650_GPIO_DOUT31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUT31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUT31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUT31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUT31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUT31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUT31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUT31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUT31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUT31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUT31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUT31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUT31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUT31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUT31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUT31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUT31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUT31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUT31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUT31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUT31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUT31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUT31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUT31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUT31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUT31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUT31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUT31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUT31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUT31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUT31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUT31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT31_0_MASK {
|
||||
CC2650_GPIO_DOUT31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUT31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUT31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUT31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUT31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUT31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUT31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUT31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUT31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUT31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUT31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUT31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUT31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUT31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUT31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUT31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUT31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUT31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUT31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUT31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUT31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUT31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOUTSET31_0 */
|
||||
enum CC2650_GPIO_DOUTSET31_0_POS {
|
||||
CC2650_GPIO_DOUTSET31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUTSET31_0_MASK {
|
||||
CC2650_GPIO_DOUTSET31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOUTCLR31_0 */
|
||||
enum CC2650_GPIO_DOUTCLR31_0_POS {
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUTCLR31_0_MASK {
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOUTTGL31_0 */
|
||||
enum CC2650_GPIO_DOUTTGL31_0_POS {
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUTTGL31_0_MASK {
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DIN31_0 */
|
||||
enum CC2650_GPIO_DIN31_0_POS {
|
||||
CC2650_GPIO_DIN31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DIN31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DIN31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DIN31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DIN31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DIN31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DIN31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DIN31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DIN31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DIN31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DIN31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DIN31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DIN31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DIN31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DIN31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DIN31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DIN31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DIN31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DIN31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DIN31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DIN31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DIN31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DIN31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DIN31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DIN31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DIN31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DIN31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DIN31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DIN31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DIN31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DIN31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DIN31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DIN31_0_MASK {
|
||||
CC2650_GPIO_DIN31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DIN31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DIN31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DIN31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DIN31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DIN31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DIN31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DIN31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DIN31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DIN31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DIN31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DIN31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DIN31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DIN31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DIN31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DIN31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DIN31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DIN31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DIN31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DIN31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DIN31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DIN31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DIN31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DIN31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DIN31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DIN31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DIN31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DIN31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DIN31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DIN31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DIN31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DIN31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOE31_0 */
|
||||
enum CC2650_GPIO_DOE31_0_POS {
|
||||
CC2650_GPIO_DOE31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOE31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOE31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOE31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOE31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOE31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOE31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOE31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOE31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOE31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOE31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOE31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOE31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOE31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOE31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOE31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOE31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOE31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOE31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOE31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOE31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOE31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOE31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOE31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOE31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOE31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOE31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOE31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOE31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOE31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOE31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOE31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOE31_0_MASK {
|
||||
CC2650_GPIO_DOE31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOE31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOE31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOE31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOE31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOE31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOE31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOE31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOE31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOE31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOE31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOE31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOE31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOE31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOE31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOE31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOE31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOE31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOE31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOE31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOE31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOE31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOE31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOE31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOE31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOE31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOE31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOE31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOE31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOE31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOE31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOE31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* EVFLAGS31_0 */
|
||||
enum CC2650_GPIO_EVFLAGS31_0_POS {
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_EVFLAGS31_0_MASK {
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
#endif /* _CC2650_GPIO_H_ */
|
||||
270
arch/arm/soc/ti_simplelink/cc2650/include/ioc.h
Normal file
270
arch/arm/soc/ti_simplelink/cc2650/include/ioc.h
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* GPIO & I/O controller registers and bit offsets for the
|
||||
* CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_IOC_H_
|
||||
#define _CC2650_IOC_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_IOC_Registers {
|
||||
CC2650_IOC_IOCFG0 = 0x0,
|
||||
CC2650_IOC_IOCFG1 = 0x4,
|
||||
CC2650_IOC_IOCFG2 = 0x8,
|
||||
CC2650_IOC_IOCFG3 = 0xC,
|
||||
CC2650_IOC_IOCFG4 = 0x10,
|
||||
CC2650_IOC_IOCFG5 = 0x14,
|
||||
CC2650_IOC_IOCFG6 = 0x18,
|
||||
CC2650_IOC_IOCFG7 = 0x1C,
|
||||
CC2650_IOC_IOCFG8 = 0x20,
|
||||
CC2650_IOC_IOCFG9 = 0x24,
|
||||
CC2650_IOC_IOCFG10 = 0x28,
|
||||
CC2650_IOC_IOCFG11 = 0x2C,
|
||||
CC2650_IOC_IOCFG12 = 0x30,
|
||||
CC2650_IOC_IOCFG13 = 0x34,
|
||||
CC2650_IOC_IOCFG14 = 0x38,
|
||||
CC2650_IOC_IOCFG15 = 0x3C,
|
||||
CC2650_IOC_IOCFG16 = 0x40,
|
||||
CC2650_IOC_IOCFG17 = 0x44,
|
||||
CC2650_IOC_IOCFG18 = 0x48,
|
||||
CC2650_IOC_IOCFG19 = 0x4C,
|
||||
CC2650_IOC_IOCFG20 = 0x50,
|
||||
CC2650_IOC_IOCFG21 = 0x54,
|
||||
CC2650_IOC_IOCFG22 = 0x58,
|
||||
CC2650_IOC_IOCFG23 = 0x5C,
|
||||
CC2650_IOC_IOCFG24 = 0x60,
|
||||
CC2650_IOC_IOCFG25 = 0x64,
|
||||
CC2650_IOC_IOCFG26 = 0x68,
|
||||
CC2650_IOC_IOCFG27 = 0x6C,
|
||||
CC2650_IOC_IOCFG28 = 0x70,
|
||||
CC2650_IOC_IOCFG29 = 0x74,
|
||||
CC2650_IOC_IOCFG30 = 0x78,
|
||||
CC2650_IOC_IOCFG31 = 0x7C
|
||||
};
|
||||
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* I/O Controller */
|
||||
/* All IOCFGx registers are the same. */
|
||||
enum CC2650_IOC_IOCFGX_POS {
|
||||
CC2650_IOC_IOCFGX_PORT_ID_POS = 0,
|
||||
CC2650_IOC_IOCFGX_IOSTR_POS = 8,
|
||||
CC2650_IOC_IOCFGX_IOCURR_POS = 10,
|
||||
CC2650_IOC_IOCFGX_SLEW_RED_POS = 12,
|
||||
CC2650_IOC_IOCFGX_PULL_CTL_POS = 13,
|
||||
CC2650_IOC_IOCFGX_EDGE_DET_POS = 16,
|
||||
CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS = 18,
|
||||
CC2650_IOC_IOCFGX_IOMODE_POS = 24,
|
||||
CC2650_IOC_IOCFGX_WU_CFG_POS = 27,
|
||||
CC2650_IOC_IOCFGX_IE_POS = 29,
|
||||
CC2650_IOC_IOCFGX_HYST_EN_POS = 30
|
||||
};
|
||||
|
||||
enum CC2650_IOC_IOCFGX_MASK {
|
||||
CC2650_IOC_IOCFGX_PORT_ID_MASK = 0x0000003F,
|
||||
CC2650_IOC_IOCFGX_IOSTR_MASK = 0x00000300,
|
||||
CC2650_IOC_IOCFGX_IOCURR_MASK = 0x00000C00,
|
||||
CC2650_IOC_IOCFGX_SLEW_RED_MASK = 0x00001000,
|
||||
CC2650_IOC_IOCFGX_PULL_CTL_MASK = 0x00006000,
|
||||
CC2650_IOC_IOCFGX_EDGE_DET_MASK = 0x00030000,
|
||||
CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK = 0x00040000,
|
||||
CC2650_IOC_IOCFGX_IOMODE_MASK = 0x07000000,
|
||||
CC2650_IOC_IOCFGX_WU_CFG_MASK = 0x18000000,
|
||||
CC2650_IOC_IOCFGX_IE_MASK = 0x20000000,
|
||||
CC2650_IOC_IOCFGX_HYST_EN_MASK = 0x40000000
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* Port-IDs available */
|
||||
enum CC2650_IOC_PORTID {
|
||||
CC2650_IOC_GPIO =
|
||||
0 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SCS =
|
||||
1 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SCK =
|
||||
2 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SDI =
|
||||
3 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SDO =
|
||||
4 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_AON_CLK32K =
|
||||
7 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AUX_IO =
|
||||
8 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_RX =
|
||||
9 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_TX =
|
||||
10 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_FSS =
|
||||
11 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_CLK =
|
||||
12 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2C_MSSDA =
|
||||
13 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2C_MSSCL =
|
||||
14 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_RX =
|
||||
15 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_TX =
|
||||
16 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_CTS =
|
||||
17 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_RTS =
|
||||
18 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_MCU_GPTM_GPTM0 =
|
||||
23 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM1 =
|
||||
24 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM2 =
|
||||
25 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM3 =
|
||||
26 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM4 =
|
||||
27 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM5 =
|
||||
28 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM6 =
|
||||
29 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM7 =
|
||||
30 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_MCU_CM3_SWV =
|
||||
32 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_RX =
|
||||
33 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_TX =
|
||||
34 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_FSS =
|
||||
35 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_CLK =
|
||||
36 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_AD0 =
|
||||
37 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_AD1 =
|
||||
38 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_WCLK =
|
||||
39 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_BCLK =
|
||||
40 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_MCLK =
|
||||
41 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_RFC_GP0 =
|
||||
47 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_RFC_GP1 =
|
||||
48 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_RFC_GP2 =
|
||||
49 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_RFC_GP3 =
|
||||
50 << CC2650_IOC_IOCFGX_PORT_ID_POS
|
||||
/* Reserved */
|
||||
};
|
||||
|
||||
/* IOSTR (drive strength) values available */
|
||||
enum CC2650_IOC_IOSTR {
|
||||
CC2650_IOC_AUTO_DRIVE_STRENGTH =
|
||||
0 << CC2650_IOC_IOCFGX_IOSTR_POS,
|
||||
CC2650_IOC_MIN_DRIVE_STRENGTH =
|
||||
1 << CC2650_IOC_IOCFGX_IOSTR_POS,
|
||||
CC2650_IOC_MED_DRIVE_STRENGTH =
|
||||
2 << CC2650_IOC_IOCFGX_IOSTR_POS,
|
||||
CC2650_IOC_MAX_DRIVE_STRENGTH =
|
||||
3 << CC2650_IOC_IOCFGX_IOSTR_POS
|
||||
};
|
||||
|
||||
/* IOCURR (IO current) values available */
|
||||
enum CC2650_IOC_IOCURR {
|
||||
CC2650_IOC_LOW_CURRENT_MODE =
|
||||
0 << CC2650_IOC_IOCFGX_IOCURR_POS,
|
||||
CC2650_IOC_HIGH_CURRENT_MODE =
|
||||
1 << CC2650_IOC_IOCFGX_IOCURR_POS,
|
||||
CC2650_IOC_EXTENDED_CURRENT_MODE =
|
||||
2 << CC2650_IOC_IOCFGX_IOCURR_POS
|
||||
};
|
||||
|
||||
/* SLEW_RED (slew rate) values available */
|
||||
enum CC2650_IOC_SLEW_RED {
|
||||
CC2650_IOC_NORMAL_SLEW_RATE =
|
||||
0 << CC2650_IOC_IOCFGX_SLEW_RED_POS,
|
||||
CC2650_IOC_REDUCED_SLEW_RATE =
|
||||
1 << CC2650_IOC_IOCFGX_SLEW_RED_POS
|
||||
};
|
||||
|
||||
/* PULL_CTL (pull-* modes) values available */
|
||||
enum CC2650_IOC_PULL_CTL {
|
||||
CC2650_IOC_PULL_DOWN =
|
||||
1 << CC2650_IOC_IOCFGX_PULL_CTL_POS,
|
||||
CC2650_IOC_PULL_UP =
|
||||
2 << CC2650_IOC_IOCFGX_PULL_CTL_POS,
|
||||
CC2650_IOC_NO_PULL =
|
||||
3 << CC2650_IOC_IOCFGX_PULL_CTL_POS
|
||||
};
|
||||
|
||||
/* EDGE_DET (edge detection) values available */
|
||||
enum CC2650_IOC_EDGE_DET {
|
||||
CC2650_IOC_NO_EDGE_DET =
|
||||
0 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
|
||||
CC2650_IOC_NEG_EDGE_DET =
|
||||
1 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
|
||||
CC2650_IOC_POS_EDGE_DET =
|
||||
2 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
|
||||
CC2650_IOC_NEG_AND_POS_EDGE_DET =
|
||||
3 << CC2650_IOC_IOCFGX_EDGE_DET_POS
|
||||
};
|
||||
|
||||
/* IOMODE values available */
|
||||
enum CC2650_IOC_IOMODE {
|
||||
CC2650_IOC_NORMAL_IO =
|
||||
0 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_INVERTED_IO =
|
||||
1 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_DRAIN_IO =
|
||||
4 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_DRAIN_INVERTED_IO =
|
||||
5 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_SOURCE_IO =
|
||||
6 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_SOURCE_INVERTED_IO =
|
||||
7 << CC2650_IOC_IOCFGX_IOMODE_POS
|
||||
};
|
||||
|
||||
/* WU_CFG (Wake-up control) values available */
|
||||
enum CC2650_IOC_WU_CFG {
|
||||
/* Values' meaning change with PORT_ID, so here we only
|
||||
* give very generic names...
|
||||
*/
|
||||
CC2650_IOC_WAKE_UP_0 =
|
||||
0 << CC2650_IOC_IOCFGX_WU_CFG_POS,
|
||||
CC2650_IOC_WAKE_UP_1 =
|
||||
1 << CC2650_IOC_IOCFGX_WU_CFG_POS,
|
||||
CC2650_IOC_WAKE_UP_2 =
|
||||
2 << CC2650_IOC_IOCFGX_WU_CFG_POS,
|
||||
CC2650_IOC_WAKE_UP_3 =
|
||||
3 << CC2650_IOC_IOCFGX_WU_CFG_POS
|
||||
};
|
||||
|
||||
/* IE (Input control) values available */
|
||||
enum CC2650_IOC_IE {
|
||||
CC2650_IOC_INPUT_DISABLED =
|
||||
0 << CC2650_IOC_IOCFGX_IE_POS,
|
||||
CC2650_IOC_INPUT_ENABLED =
|
||||
1 << CC2650_IOC_IOCFGX_IE_POS
|
||||
};
|
||||
|
||||
/* HYST_EN (Hysteresis control) values available */
|
||||
enum CC2650_IOC_HYST_EN {
|
||||
CC2650_IOC_HYSTERESIS_DISABLED =
|
||||
0 << CC2650_IOC_IOCFGX_HYST_EN_POS,
|
||||
CC2650_IOC_HYSTERESIS_ENABLED =
|
||||
1 << CC2650_IOC_IOCFGX_HYST_EN_POS
|
||||
};
|
||||
|
||||
#endif /* _CC2650_IOC_H_ */
|
||||
108
arch/arm/soc/ti_simplelink/cc2650/include/prcm.h
Normal file
108
arch/arm/soc/ti_simplelink/cc2650/include/prcm.h
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Offsets for the Power, Reset, and Clock Management module
|
||||
* registers, in the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_PRCM_H_
|
||||
#define _CC2650_PRCM_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_PRCM_Registers {
|
||||
CC2650_PRCM_CLKLOADCTL = 0x28,
|
||||
CC2650_PRCM_SECDMACLKGR = 0x3C,
|
||||
CC2650_PRCM_GPIOCLKGR = 0x48,
|
||||
CC2650_PRCM_UARTCLKGR = 0x6C,
|
||||
CC2650_PRCM_UARTCLKGS = 0x70,
|
||||
CC2650_PRCM_UARTCLKGDS = 0x74,
|
||||
CC2650_PRCM_PDCTL0 = 0x12C,
|
||||
CC2650_PRCM_PDSTAT0 = 0x140
|
||||
};
|
||||
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* CLKLOADCTL */
|
||||
enum CC2650_PRCM_CLKLOADCT_POS {
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_POS = 0,
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_DONE_POS = 1
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_CLKLOADCTL_MASK {
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_MASK = 0x00000001,
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_DONE_MASK = 0x00000002
|
||||
};
|
||||
|
||||
/* SECDMACLKGR */
|
||||
enum CC2650_PRCM_SECDMACLKGR_POS {
|
||||
CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_POS = 1
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_SECDMACLKGR_MASK {
|
||||
CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_MASK = 0x00000002
|
||||
};
|
||||
|
||||
/* GPIOCLKGR */
|
||||
enum CC2650_PRCM_GPIOCLKGR_POS {
|
||||
CC2650_PRCM_GPIOCLKGR_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_GPIOCLKGR_MASK {
|
||||
CC2650_PRCM_GPIOCLKGR_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* UARTCLKGR */
|
||||
enum CC2650_PRCM_UARTCLKGR_POS {
|
||||
CC2650_PRCM_UARTCLKGR_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_UARTCLKGR_MASK {
|
||||
CC2650_PRCM_UARTCLKGR_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* UARTCLKGS */
|
||||
enum CC2650_PRCM_UARTCLKGS_POS {
|
||||
CC2650_PRCM_UARTCLKGS_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_UARTCLKGS_MASK {
|
||||
CC2650_PRCM_UARTCLKGS_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* UARTCLKGDS */
|
||||
enum CC2650_PRCM_UARTCLKGDS_POS {
|
||||
CC2650_PRCM_UARTCLKGDS_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_UARTCLKGDS_MASK {
|
||||
CC2650_PRCM_UARTCLKGDS_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* PDCTL0 */
|
||||
enum CC2650_PRCM_PDCTL0_POS {
|
||||
CC2650_PRCM_PDCTL0_SERIAL_ON_POS = 1,
|
||||
CC2650_PRCM_PDCTL0_PERIPH_ON_POS = 2
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_PDCTL0_MASK {
|
||||
CC2650_PRCM_PDCTL0_SERIAL_ON_MASK = 0x00000002,
|
||||
CC2650_PRCM_PDCTL0_PERIPH_ON_MASK = 0x00000004
|
||||
};
|
||||
|
||||
/* PDSTAT0 */
|
||||
enum CC2650_PRCM_PDSTAT0_POS {
|
||||
CC2650_PRCM_PDSTAT0_RFC_ON_POS = 0,
|
||||
CC2650_PRCM_PDSTAT0_SERIAL_ON_POS = 1,
|
||||
CC2650_PRCM_PDSTAT0_PERIPH_ON_POS = 2
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_PDSTAT0_MASK {
|
||||
CC2650_PRCM_PDSTAT0_RFC_ON_MASK = 0x00000001,
|
||||
CC2650_PRCM_PDSTAT0_SERIAL_ON_MASK = 0x00000002,
|
||||
CC2650_PRCM_PDSTAT0_PERIPH_ON_MASK = 0x00000004
|
||||
};
|
||||
|
||||
#endif /* _CC2650_PRCM_H_ */
|
||||
7
arch/arm/soc/ti_simplelink/cc2650/linker.ld
Normal file
7
arch/arm/soc/ti_simplelink/cc2650/linker.ld
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* linker.ld - Linker command/script file
|
||||
*/
|
||||
|
||||
#include <arch/arm/cortex_m/scripts/linker.ld>
|
||||
146
arch/arm/soc/ti_simplelink/cc2650/soc.c
Normal file
146
arch/arm/soc/ti_simplelink/cc2650/soc.c
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Basic initialization for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#include <toolchain/gcc.h>
|
||||
#include <init.h>
|
||||
#include <sys_io.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
|
||||
#define CCFG_SIZE 88
|
||||
|
||||
/* The bootloader of the SoC (in ROM) reads configuration
|
||||
* data (CCFG) at a fixed address (last page of flash).
|
||||
* The most notable information being whether to run the
|
||||
* code stored in flash or not.
|
||||
*
|
||||
* We put configuration data in a specific section so that
|
||||
* the linker script can map it accordingly.
|
||||
*/
|
||||
const u32_t
|
||||
__ti_ccfg_section
|
||||
ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = {
|
||||
0x00008001, /* EXT_LF_CLK: default values */
|
||||
0xFF13FFFF, /* MODE_CONF_1: default values */
|
||||
0x0058FFFF, /* SIZE_AND_DIS_FLAGS: 88 bytes long, no external osc. */
|
||||
0xFFFFFFFF, /* MODE_CONF: default values */
|
||||
0xFFFFFFFF, /* VOLT_LOAD_0: default values */
|
||||
0xFFFFFFFF, /* VOLT_LOAD_1: default values */
|
||||
0xFFFFFFFF, /* RTC_OFFSET: default values */
|
||||
0xFFFFFFFF, /* FREQ_OFFSET: default values */
|
||||
0xFFFFFFFF, /* IEEE_MAC_0: use MAC address from FCFG */
|
||||
0xFFFFFFFF, /* IEEE_MAC_1: use MAC address from FCFG */
|
||||
0xFFFFFFFF, /* IEEE_BLE_0: use BLE address from FCFG */
|
||||
0xFFFFFFFF, /* IEEE_BLE_1: use BLE address from FCFG */
|
||||
/* BL_CONFIG: disable backdoor and bootloader,
|
||||
* default pin, default active level (high)
|
||||
*/
|
||||
CC2650_CCFG_BACKDOOR_DISABLED |
|
||||
(0xFF << CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS) |
|
||||
(0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS) |
|
||||
0x00FE0000 | /* reserved */
|
||||
CC2650_CCFG_BOOTLOADER_DISABLED,
|
||||
0xFFFFFFFF, /* ERASE_CONF: default values (banks + chip erase) */
|
||||
/* CCFG_TI_OPTIONS: disable TI failure analysis */
|
||||
CC2650_CCFG_TI_FA_DISABLED |
|
||||
0xFFFFFF00, /* reserved */
|
||||
0xFFC5C5C5, /* CCFG_TAP_DAP_0: default values */
|
||||
0xFFC5C5C5, /* CCFG_TAP_DAP_1: default values */
|
||||
/* IMAGE_VALID_CONF: authorize program on flash to run */
|
||||
CC2650_CCFG_IMAGE_IS_VALID,
|
||||
/* Make all flash chip programmable + erasable
|
||||
* (which is default)
|
||||
*/
|
||||
0xFFFFFFFF, /* CCFG_PROT_31_0 */
|
||||
0xFFFFFFFF, /* CCFG_PROT_61_32 */
|
||||
0xFFFFFFFF, /* CCFG_PROT_95_64 */
|
||||
0xFFFFFFFF /* CCFG_PROT_127_96 */
|
||||
};
|
||||
|
||||
/* PRCM Registers */
|
||||
static const u32_t clkloadctl =
|
||||
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_CLKLOADCTL);
|
||||
static const u32_t secdmaclkgr =
|
||||
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_SECDMACLKGR);
|
||||
static const u32_t gpioclkgr =
|
||||
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_GPIOCLKGR);
|
||||
static const u32_t pdctl0 =
|
||||
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_PDCTL0);
|
||||
static const u32_t pdstat0 =
|
||||
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_PDSTAT0);
|
||||
static const u32_t uartclkgr =
|
||||
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_UARTCLKGR);
|
||||
|
||||
/* Setup power and clock for needed hardware modules. */
|
||||
static void setup_modules_prcm(void)
|
||||
{
|
||||
#if defined(CONFIG_GPIO_CC2650) || \
|
||||
defined(CONFIG_CC2650_TRNG_RANDOM_GENERATOR) || \
|
||||
defined(CONFIG_SERIAL)
|
||||
|
||||
/* Setup power */
|
||||
#if defined(CONFIG_GPIO_CC2650) || defined(CONFIG_CC2650_TRNG_RANDOM_GENERATOR)
|
||||
sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_PERIPH_ON_POS);
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL
|
||||
sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_SERIAL_ON_POS);
|
||||
#endif
|
||||
|
||||
/* Setup clocking */
|
||||
#ifdef CONFIG_GPIO_CC2650
|
||||
sys_set_bit(gpioclkgr, CC2650_PRCM_GPIOCLKGR_CLK_EN_POS);
|
||||
#endif
|
||||
#ifdef CONFIG_CC2650_TRNG_RANDOM_GENERATOR
|
||||
sys_set_bit(secdmaclkgr, CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_POS);
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL
|
||||
sys_set_bit(uartclkgr, CC2650_PRCM_UARTCLKGR_CLK_EN_POS);
|
||||
#endif
|
||||
/* Reload clocking configuration for device */
|
||||
sys_set_bit(clkloadctl, CC2650_PRCM_CLKLOADCTL_LOAD_POS);
|
||||
|
||||
/* Wait for power to be completely on, to avoid bus faults
|
||||
* when accessing modules' registers.
|
||||
*/
|
||||
#if defined(CONFIG_GPIO_CC2650) || defined(CONFIG_CC2650_TRNG_RANDOM_GENERATOR)
|
||||
while (!(sys_read32(pdstat0) &
|
||||
BIT(CC2650_PRCM_PDSTAT0_PERIPH_ON_POS))) {
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL)
|
||||
while (!(sys_read32(pdstat0) &
|
||||
BIT(CC2650_PRCM_PDSTAT0_SERIAL_ON_POS))) {
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static int ti_cc2650(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
NMI_INIT();
|
||||
setup_modules_prcm();
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(ti_cc2650, PRE_KERNEL_1, 0);
|
||||
|
||||
int bit_is_set(u32_t reg, u8_t bit)
|
||||
{
|
||||
return sys_read32(reg) & BIT(bit);
|
||||
}
|
||||
25
arch/arm/soc/ti_simplelink/cc2650/soc.h
Normal file
25
arch/arm/soc/ti_simplelink/cc2650/soc.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* General header for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_SOC_H_
|
||||
#define _CC2650_SOC_H_
|
||||
|
||||
#include <misc/util.h>
|
||||
#include "include/ccfg.h"
|
||||
#include "include/gpio.h"
|
||||
#include "include/ioc.h"
|
||||
#include "include/prcm.h"
|
||||
|
||||
|
||||
/* Helper functions and macros */
|
||||
|
||||
#define REG_ADDR(Base, Offset) (u32_t)(Base + (u32_t)Offset)
|
||||
|
||||
int bit_is_set(u32_t reg, u8_t bit);
|
||||
|
||||
|
||||
#endif /* _CC2650_SOC_H_ */
|
||||
66
dts/arm/ti/cc2650.dtsi
Normal file
66
dts/arm/ti/cc2650.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Device Tree include file for CC2650 SoC from Texas Instruments.
|
||||
*/
|
||||
|
||||
#include "armv7-m.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-m3";
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory {
|
||||
compatible = "sram";
|
||||
reg = <0x20000000 0x5000>;
|
||||
};
|
||||
|
||||
flash0: serial-flash {
|
||||
compatible = "serial-flash";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
gpioa: gpio@40022000 {
|
||||
compatible = "ti,cc2650-gpio";
|
||||
reg = <0x40022000 0xE4>;
|
||||
interrupts = <0 0>;
|
||||
zephyr,irq-prio = <0>;
|
||||
status = "disabled";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
};
|
||||
|
||||
pinmux_a: pinmux@40081000 {
|
||||
compatible = "ti,cc2650-pinmux";
|
||||
reg = <0x40081000 0x80>;
|
||||
};
|
||||
|
||||
prcm0: prcm@40082000 {
|
||||
compatible = "ti,cc2650-prcm";
|
||||
reg = <0x40082000 0x228>;
|
||||
};
|
||||
|
||||
trng0: trng@40028000 {
|
||||
compatible = "ti,cc2650-trng";
|
||||
reg = <0x40028000 0x1FFC>;
|
||||
interrupts = <33 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@40001000 {
|
||||
compatible = "ti,stellaris-uart";
|
||||
reg = <0x40001000 0x4C>;
|
||||
interrupts = <5 0>, <6 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
22
dts/arm/yaml/ti,cc2650-prcm.yaml
Normal file
22
dts/arm/yaml/ti,cc2650-prcm.yaml
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
---
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
title: TI CC2650 PRCM
|
||||
version: 0.1
|
||||
|
||||
description: >
|
||||
This binding gives a base representation of the TI CC2650
|
||||
Power, Reset, and Clock control Module.
|
||||
|
||||
properties:
|
||||
- compatible:
|
||||
type: string
|
||||
category: required
|
||||
description: compatible strings
|
||||
constraint: "ti,cc2650-prcm"
|
||||
|
||||
- reg:
|
||||
type: array
|
||||
description: mmio register space
|
||||
generation: define
|
||||
category: required
|
||||
...
|
||||
Loading…
Reference in a new issue