dts: add EOS S3 devicetree

Add basic devicetree for EOS S3 SoCs.

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>

CODEOWNERS

@@ -280,6 +280,7 @@
 /dts/arm/broadcom/                        @sbranden
 /dts/arm/infineon/                        @parthitce
 /dts/arm/qemu-virt/                       @carlocaione
+/dts/arm/quicklogic/                      @wtatarski @kowalewskijan @kgugala
 /dts/arm/st/                              @erwango
 /dts/arm/ti/cc13?2*                       @bwitherspoon
 /dts/arm/ti/cc26?2*                       @bwitherspoon

dts/arm/quicklogic/quicklogic_eos_s3.dtsi

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_K(512)>;
+	};
+
+	uartclk: uart-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <5120000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		uart0: uart@40010000 {
+			compatible = "arm,pl011";
+			reg = <0x40010000 DT_SIZE_K(4)>;
+			clocks = <&uartclk>;
+			interrupts = <7 3>;
+			interrupt-names = "rx";
+			label = "UART_0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

dts/bindings/vendor-prefixes.txt

@@ -336,6 +336,7 @@ qemu	QEMU, a generic and open source machine emulator and virtualizer
 qi	Qi Hardware
 qiaodian	QiaoDian XianShi Corporation
 qnap	QNAP Systems, Inc.
+quicklogic	QuickLogic Corp.
 radxa	Radxa
 raidsonic	RaidSonic Technology GmbH
 ralink	Mediatek/Ralink Technology Corp.