soc: rt5xx: Enable NXP MRT
Enable NXP MRT on RT5xx soc and MIMXRT595_EVK board Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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@ -478,3 +478,7 @@ zephyr_udc0: &usbhs {
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dmas = <&smartdma>;
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dma-names = "smartdma";
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};
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&mrt_channel0 {
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status = "okay";
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};
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@ -578,6 +578,38 @@
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#mbox-cells = <1>;
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status = "disabled";
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};
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mrt: mrt@2d000 {
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compatible = "nxp,mrt";
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reg = <0x2d000 0x100>;
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interrupts = <9 0>;
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num-channels = <4>;
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num-bits = <24>;
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clocks = <&clkctl1 MCUX_MRT_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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mrt_channel0: mrt_channel@0 {
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compatible = "nxp,mrt-channel";
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reg = <0>;
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status = "disabled";
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};
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mrt_channel1: mrt_channel@1 {
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compatible = "nxp,mrt-channel";
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reg = <1>;
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status = "disabled";
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};
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mrt_channel2: mrt_channel@2 {
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compatible = "nxp,mrt-channel";
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reg = <2>;
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status = "disabled";
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};
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mrt_channel3: mrt_channel@3 {
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compatible = "nxp,mrt-channel";
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reg = <3>;
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status = "disabled";
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};
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};
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};
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&flexspi {
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@ -419,6 +419,10 @@ void __weak rt5xx_clock_init(void)
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CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1);
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#endif
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#if CONFIG_COUNTER_NXP_MRT
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RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn);
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#endif
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/* Set SystemCoreClock variable. */
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SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
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