soc: rt5xx: Enable NXP MRT

Enable NXP MRT on RT5xx soc and MIMXRT595_EVK board

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder 2023-11-03 10:36:15 -05:00 committed by Carles Cufí
parent 8257ff8f6a
commit ff83745c9a
3 changed files with 40 additions and 0 deletions

View file

@ -478,3 +478,7 @@ zephyr_udc0: &usbhs {
dmas = <&smartdma>;
dma-names = "smartdma";
};
&mrt_channel0 {
status = "okay";
};

View file

@ -578,6 +578,38 @@
#mbox-cells = <1>;
status = "disabled";
};
mrt: mrt@2d000 {
compatible = "nxp,mrt";
reg = <0x2d000 0x100>;
interrupts = <9 0>;
num-channels = <4>;
num-bits = <24>;
clocks = <&clkctl1 MCUX_MRT_CLK>;
#address-cells = <1>;
#size-cells = <0>;
mrt_channel0: mrt_channel@0 {
compatible = "nxp,mrt-channel";
reg = <0>;
status = "disabled";
};
mrt_channel1: mrt_channel@1 {
compatible = "nxp,mrt-channel";
reg = <1>;
status = "disabled";
};
mrt_channel2: mrt_channel@2 {
compatible = "nxp,mrt-channel";
reg = <2>;
status = "disabled";
};
mrt_channel3: mrt_channel@3 {
compatible = "nxp,mrt-channel";
reg = <3>;
status = "disabled";
};
};
};
&flexspi {

View file

@ -419,6 +419,10 @@ void __weak rt5xx_clock_init(void)
CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1);
#endif
#if CONFIG_COUNTER_NXP_MRT
RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn);
#endif
/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;