soc: arm: gigadevice: add initial support for gd32e50x series

Add initial support for GD32E50X series (only GD32507X for now).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

soc/arm/gigadevice/gd32e50x/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2022, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)

soc/arm/gigadevice/gd32e50x/Kconfig.defconfig.gd32e507

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+# Copyright (c) 2022 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_GD32E507
+
+config SOC
+	default "gd32e507"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config NUM_IRQS
+	default 88
+
+endif # SOC_GD32E507

soc/arm/gigadevice/gd32e50x/Kconfig.defconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2022, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32E50X
+
+source "soc/arm/gigadevice/gd32e50x/Kconfig.defconfig.gd32*"
+
+config SOC_SERIES
+	default "gd32e50x"
+
+endif # SOC_SERIES_GD32E50X

soc/arm/gigadevice/gd32e50x/Kconfig.series

@@ -0,0 +1,13 @@
+# Copyright (c) 2022, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32E50X
+	bool "GigaDevice GD32E50X series Cortex-M33 MCU"
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_CORTEX_M33
+	select SOC_FAMILY_GD32_ARM
+	select GD32_HAS_AFIO_PINMUX
+	help
+	  Enable support for GigaDevice GD32E50X MCU series

soc/arm/gigadevice/gd32e50x/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2022, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32E50X MCU Selection"
+	depends on SOC_SERIES_GD32E50X
+
+	config SOC_GD32E507
+		bool "gd32e507"
+
+endchoice

soc/arm/gigadevice/gd32e50x/linker.ld

@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/gigadevice/gd32e50x/soc.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/irq.h>
+
+static int gd32e50x_soc_init(const struct device *dev)
+{
+	uint32_t key;
+
+	ARG_UNUSED(dev);
+
+	key = irq_lock();
+
+	SystemInit();
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(gd32e50x_soc_init, PRE_KERNEL_1, 0);

soc/arm/gigadevice/gd32e50x/soc.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_ARM_GIGADEVICE_GD32E50X_SOC_H_
+#define _SOC_ARM_GIGADEVICE_GD32E50X_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <gd32e50x.h>
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _SOC_ARM_GIGADEVICE_GD32E50X_SOC_H_ */