Some targets do not give EoD at the end of a register read. They will
auto increment their address pointer on to the next address, but that
may not be of interest to the application where the buffer size will
only be set to the size of only that register. If the target, does
not give an EoD, then the Controller will give an Abort... but this
should not be treated as an error in this case.
There is still however a case where an abort Error shall still be
considered as an error. Athough the driver does not support it yet,
threshold interrupts are to be used if the length of the buffer
exceeds the size of the fifo. There could be the case where the
cpu can not get around fast enough to pop out data out of the rx
fifo and it will fill up. The controller will just give an abort
as it can not take any more data.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The command response buffer will return the total number of bytes
transfered. This will write back to the pointer which is to contain
the number of bytes sent or received.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This renames the I2C 'DCR' mode to 'LVR' as that is the variable it
should be looking at and not the dcr value. This also fixes the get
'lvr' mode argument.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Previously, the idle bit would be read for X amount of times. This
could vary alot depend on the CPU speed. Timeout is now to happen
from the cycle time.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
For example, if a driver needed to reserve address before it does a
ENTDAA, it would need to get free address in a loop, but the get
free address func would return the same address everytime. It needs
the start address, which would be the last free address it go, to
be passed in to get the next free address.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The Cadence I3C was not building with CONFIG_I3C_USE_IBI, this fixes
the build and will give a small code size reduction when enabled.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
If a transfer happen in rapid sucession. It was possible for
the core to not be ready to accept another command. Poll on
the idle status bit until the core is ready to accept new data.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Due to a bug, after a completed transfer happen. Only the first
command response error was read. This fixes the issue so all
commands are read for if an error occurred.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
When a controller is running at full SDR speed at 12.5MHz, there needs
to be enough time for the processor get around to writing more data in
the fifo. Previously at -1 the size, this was enough for 1MHz with a
decent processor, but not enough at a 12.5MHz SCL.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The cadence i3c ip requires it's retaining registers to be updated
when a device is detached or attached.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This adds the reattach api necessary for writing the i3c retaining
registers within the cdns i3c when the dynamic address changes.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
