Commit graph

51 commits

Author SHA1 Message Date
Daniel Leung 9a6e32f87c mm: rename struct mem_drv_bank to sys_mm_drv_bank
Simply to put them into correct namespace as the struct is
part of public API.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-11-21 08:42:01 +00:00
Daniel Leung ca1aae6183 mm: intel_adsp_mtl_tlb: move SRAM_BANK_PAGE_NUM in driver
The macro SRAM_BANK_PAGE_NUM is specfic to the mtl_tlb
driver and is not universal. So move that from public
header into the driver.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-11-21 08:42:01 +00:00
Daniel Leung c972ef1a0f kernel: mm: move kernel mm functions under kernel includes
This moves the k_* memory management functions from sys/ into
kernel/ includes, as there are kernel public APIs. The z_*
functions are further separated into the kernel internal
header directory.

Also made a quick change to doxygen to group sys_mem_* into
the OS Memory Management group so they will appear in doc.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-11-20 09:19:14 +01:00
Peter Mitsis baea37aeb4 kernel: Re-factor sys_mem_blocks definition
Rearranges the sys_mem_blocks fields so that information that describes
how much of the memory block is used is co-located. This will allow
easier of its statistics into the object core statistics reporting
framework.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-09-30 08:04:14 +03:00
Yong Cong Sin 0538411c09 drivers: mm: refine includes of the header
Refines the `system_mm.h` to include `zephyr/types.h` instead
of `zephyr/kernel.h` as that is all it needs.

Updated the includes of `mm_drv_ti_rat.c` accordingly.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-26 15:09:12 +02:00
Daniel Baluta b4998c357e mm_drv: tlb: Fix compile time warning
This fixes the following compile time warning;

drivers/mm/mm_drv_intel_adsp_mtl_tlb.c: In function 'sys_mm_drv_mm_init':
include/zephyr/sys/__assert.h:44:52: error: format '%p' expects argument
of type 'void *', but argument 2 has type
'long unsigned int' [-Werror=format=]
__ASSERT_PRINT("\t" fmt "\n", ##__VA_ARGS__)

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2023-09-22 09:24:02 +02:00
Peter Ujfalusi ab0ed57711 mm: intel_adsp_tlb: Handle address space conversion warnings
There are various call to z_soc_cached_ptr() which returns values
in the cached address space and are stored in temporary variables
that are not marked as in the cached address space. This results
in sparse complaining about discarding the cached address space
attribute. These temporary variables are then passed to other
internal memory management related functions which do not have
the concept of cached address space (as it is currently Xtensa
specific). Because of this, we cannot change the signature of
these functions. Instead, we force a change of address space
when those temporary variables are being assigned to suppress
sparse warnings.

Reported-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2023-08-23 14:45:14 +02:00
L Lakshmanan 8fca1cdb29 drivers: mm: Fix macro call in RAT driver
The macro used in an assert statement in the `sys_mm_drv_page_phys_get()`
function was using an older version of the naming scheme, fixed now.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-14 09:37:53 +02:00
L Lakshmanan 934c6d7b33 drivers: mm: Fix cast warnings on build for RAT
Removed the unneccessary casts in the functions to remove warnings
during build for SoCs using RAT. Functionality reamins the same,
tested on board.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-11 18:20:26 +00:00
L Lakshmanan 7fc6e331d8 drivers: mm: Add support for TI RAT module using system_mm API
Added Region based Address Translation (RAT) module driver. Required by
a few Texas Instruments SoCs to fucntion. Uses
sys_mm_drv_page_phys_get() API with device_map() for address translation.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-11 09:44:48 +02:00
Jaroslaw Stelter 0bf467bbcd mm_drv: tlb: Fix context save for remapped pages
In case of remapped reference counter for physical page
is differ to zero, but TLB entry for virtual address equal to
physical address will be disabled. Valid entry will be somewhere
in virtual space where particular physical page is remapped.

Since in adsp_mm_save_context() routine we go through physical
memory range, we need to include these pages in context save loop.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-07-10 09:27:31 +02:00
Jaroslaw Stelter 225e8c09ac mm_drv: tlb: Fix driver tests
Previous fix https://github.com/zephyrproject-rtos/zephyr/pull/58891
introduced failure in driver tests suite. This patch corrects the error
and reverts max_mapped_page field definition.
Adds max_mapped_pages stats reset after unmaping of unused memory.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-06-22 17:23:56 -04:00
Jaroslaw Stelter faadbc42ee mm_drv: tlb: Fix mapped page in bank calculation
The initial implementation was broken during improvements.
There was incorrect assumption that all pages are unmapped at
initials state. In reality at the beginning whole memory is
powered on, so we should mark all pages as mapped. Later in
initialization code unused pages are unmapped and if after this
some banks become empty (all pages unmapped), the power is
switched off.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-06-20 14:00:59 -04:00
Anas Nashif 6388f5f106 xtensa: use sys_cache API instead of custom interfaces
Use sys_cache instead of custom and internal APIs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-26 07:31:22 -04:00
Anas Nashif e195739565 intel_adsp: move utils to a new header
Move utility code into a new header and cleanup soc.h

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-26 07:31:22 -04:00
Gerard Marull-Paretas 0ebe14beb4 sys: util: migrate all files to DIV_ROUND_UP
ceiling_fraction is deprecated, use DIV_ROUND_UP.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-11 12:00:37 +02:00
Henrik Brix Andersen c41dd36de2 drivers: kconfig: unify menuconfig title strings
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".

Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-28 15:06:06 +02:00
Guennadi Liakhovetski 4e822592b8 mm: intel: adsp: simplify code in mm_drv_intel_adsp_regions.c
temporary_table is a trivial copy of virtual_memory_regions, it isn't
clear why it's needed. All the more that it's freely mixed with
virtual_memory_regions itself. Also change a variable name to avoid
confusion and improve indentation.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-03-23 16:31:08 -04:00
Peter Mitsis 5760523091 drivers: mm: Use mm_drv_bank module
Updates the meteor-lake TLB MM driver to use the memory bank module
to track page usage statistics.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-02-20 09:48:44 +01:00
Peter Mitsis 87899c07f7 drivers: mm: Add module for tracking page usage
Adds a module for tracking page usage within a memory bank.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-02-20 09:48:44 +01:00
Marcin Szkudlinski 44222b7dfc mtl: bugfix: tlb driver should allow remapping all unused pages
UNUSED_L2_START_ALIGNED is a marker of first page not used by the
linker. Starting from this page, the memory may be re-mapped.
assertion <= is banning remapping of the first unused page
changing to <

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2023-02-03 20:59:08 +09:00
Daniel Leung 422250d3b1 mm: intel_adsp_mtl_tlb: suppress sparse address space warnings
There are various call to z_soc_cached_ptr() which returns values
in the cached address space and are stored in temporary variables
that are not marked as in the cached address space. This results
in sparse complaining about discarding the cached address space
attribute. These temporary variables are then passed to other
internal memory management related functions which do not have
the concept of cached address space (as it is currently Xtensa
specific). Because of this, we cannot change the signature of
these functions. Instead, we force a change of address space
when those temporary variables are being assigned to suppress
sparse warnings.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-01-19 06:52:23 -05:00
Adrian Warecki 0e17395bbf mtl: drv: mm: tlb: Add reporting of memory usage to PMC
The number of HPSRAM memory blocks in use is reported to the
PMC via the sideband channel supported by the communication widget.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-01-18 10:47:21 +01:00
Jakub Dabek 72f626046d memory manager: add region calculation for virtual memory
Add region calculations and implementation of
sys_mm_drv_query_memory_regions to pass calculated regions down
the line.

Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
2022-12-20 07:03:55 -05:00
Jakub Dabek 9531f96627 memory manager: refactor
Separate definitions from function code by creating header file for statics
managment.

Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
2022-12-20 07:03:55 -05:00
Ederson de Souza 9c55195235 drivers/mm: Only remap unused RAM on Kconfig on Intel ADSP MTL
Remapping by default can confuse things that dynamically manage RAM,
such as newlib heap - since unused memory will be powered off by
default. So this patch shields this behaviour behind a non-default
Kconfig.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-11-29 18:03:09 -05:00
Carles Cufi 4796ffee7a drivers: mm: Move mm_drv_intel_adsp_mtl_tlb to zephyr/
This file was mistakenly placed in include/ instead of include/zephyr.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2022-11-21 20:43:50 +09:00
Marcin Szkudlinski 84c09433b5 mtl: soc: TLB driver provides required size of L3 storage buffer
TLB driver knows the required number of bytes for HPSRAM
storage during power off state.

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2022-11-18 13:00:04 -05:00
Marcin Szkudlinski 3ee8bf7053 mtl: soc: add TLB driver context save to platform PowerManagement
Connect the TLB context save to MTL suspend power flow

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2022-11-18 13:00:04 -05:00
Marcin Szkudlinski 540f6d1dc5 mtl: drivers: tlb driver cleanup
a small cleanup in the code, preaparation for memory context save

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-11-18 13:00:04 -05:00
Jakub Dabek b052143077 memory manager: Add runtime memory discovery
Add runtime physical memory discovery. This allows platforms with
different physical memory sizes to use the same driver for memory
management.

Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
2022-11-07 06:44:05 -05:00
Anas Nashif 6c3277eada intel_adsp: ace: rename namespace: MTL -> ACE
MTL is just one platform and this code is going to be used in multiple
platforms currently under development, so reduce the confusion and move
to a common namespace.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Anas Nashif 0869e62539 intel_adsp: cleanup ace_v1x-regs.h more and prep for removal
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 12:50:05 -04:00
Ederson de Souza edd524b4e3 drivers/mm: Add API to query memory regions
Some systems may need to query the available memory regions in runtime.
For those, this patch adds a simple API that memory management drivers
can implement to provide such discovery.

A small test also added to exercise the default, empty implementation.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-01 14:52:29 -04:00
Flavio Ceolin 45465708f0 soc: intel_adsp: Add ACE soc series
ACE15_MTPM is one SOC from the ACE series. Organize
it following cavs pattern.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:03:59 -04:00
Ederson de Souza 67a6837efd drivers/mm: Remove redundant ifdef for MTL ADSP TBL implementation
An `ifdef CONFIG_SOC_SERIES_INTEL_ACE1X` currently always evaluates to
true, as `drivers/mm/mm_drv_intel_adsp_mtl_tlb.c` is only built when
`CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y`, which depends on
`CONFIG_SOC_SERIES_INTEL_ACE1X`. So remove the ifdef.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza 03a947850d drivers/mm: Get some bit configurations from DTS instead of SoC version
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Kumar Gala 0ee0269848 drivers: mm: Update Kconfig
* Utilize DT_HAS_<COMPAT>_ENABLED for devicetree based drivers

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-31 11:17:37 -05:00
Kumar Gala fab8d25fd3 drivers: mm: Add dts binding specific for ADSP Meteor Lake TLB
Add a specific compatiable and binding for intel,adsp-mtl-tlb.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-31 11:17:37 -05:00
Anas Nashif 43371d0414 intel_adsp: move cavs to be a series
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-25 16:50:24 -04:00
Anas Nashif af3d5331a1 intel-adsp: migrate cavs-mem.h to adsp_memory.h
Move header and make it soc specific.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Jaroslaw Stelter fe5ed68356 soc: ace_v1x: check physical memory bounds on page unmap.
This patch fix issue with unmapping of virtual addresses mapped
to non-existing physical memory. MTL TLB table is initialised with
1:1 mapping, however virtual space is much wider than available
physical space. We should not try to free and manage of power for
non-existing physical pages.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2022-07-21 05:32:03 -04:00
Jaroslaw Stelter afb156a1eb soc: ace_v1x: unmap entire unused virtual space
This patch corrects the initial unmapping of unused l2 memory
to unmap until the end of virtual address space instead
of unmapping until the end of l2 physical memory.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2022-07-13 09:46:48 -05:00
Jaroslaw Stelter 8b598539f2 soc: ace_v1x: correct the move_region behavior
This patch introduces sys_mm_drv_move_region implementation
which stops usage of the sys_mm_drv_simple_move_region.
The sys_mm_drv_simple_move_region is unsuitable becuase
it iterates through physical pages in linear fashion.
The new implementation queries the tlb for each virtual
page of the requested region to find the physical page
to be remapped.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2022-07-13 09:46:48 -05:00
Jaroslaw Stelter cf24124efa mm: introduce update memory flags api
There are cases when attributes of mapped virtual memory need
to be updated. E.g. in case there is loadable library/module
code loaded to the l2 memory then memory needs to be read-write.
After the code is loaded and is ready to be executed then
attributes of mapped memory should be updated to
read-only/executable without loosing memory contents.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2022-07-13 15:53:14 +02:00
Anas Nashif 3ccafb1af3 intel_adsp: meteorlake: add memory driver
Add TLB driver specific for Meteorlake.

Add missing kconfig resource and fix include path
add hpsram power up and ref counter

Use memblock to track physical page usage in mtl tlb driver. The
applications that will be using the tlb memory driver should not
track the physical page mapping to virtual address space:
 - adds an option to use the phys argument value of 0 to tell the
   driver to autonomously assign physical pages upon map request
 - makes the tlb driver use memblock to track mapped physical pages

Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Co-authored-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 15:11:07 -04:00
Gerard Marull-Paretas fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Maureen Helm 5769dffc01 drivers: mm: Use dt_compat_enabled for Intel ADSP TLB driver default
Enables the Intel TLB driver by default when the MM driver class is
enabled (CONFIG_MM_DRV=y) and a compatible devicetree node
("intel,adsp-tlb") is enabled.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-04-25 11:41:31 -07:00
Nazar Kazakov f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
Daniel Leung 9e688e3956 drivers: mm: add driver for Intel Audio DSP
This adds the driver for the memory mapping hardware
on Intel Audio DSP.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-18 19:18:30 -05:00