Commit graph

3 commits

Author SHA1 Message Date
Laurentiu Mihalcea 41289dac06 drivers: dma: dma_nxp_edma: add function for channel filtering
The point of this commit is to allow users to request specific
channels. The following code snippet shows how this may now be
achieved:

	int requested_channel = 5;
	int ret = dma_request_channel(dev, &requested_channel);

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-02-09 16:20:34 +00:00
Laurentiu Mihalcea c07d987431 drivers: dma: dma_nxp_edma: query channel number from HAL config
Currently, the number of channels supported by the controlled
is computed based on the size of the channel array. This
works well only if there's no gaps (i.e: "dma-channels" property
is used or "valid-channels" property is used with contiguous
channels) but will break if there are any gaps. For instance,
if the user wants to use channels 16 and 17 and specifies them
through the "valid-channels" property, they won't be allowed
to do so because dma_request_channels() will stop at channel 1.
As such, to fix this, simply use the number of channels from
the HAL configuration which is the maximum number of channels.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-02-09 16:20:34 +00:00
Laurentiu Mihalcea 6abc5921e1 drivers: dma: Introduce driver for NXP's eDMA IP
This commit introduces a driver for NXP's eDMA IP.

The main reasons for introducing a new driver are the following:

	1) The HAL EDMA wrappers don't support well different
	eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new
	revision had to be introduced, thus requiring a new Zephyr
	driver.

	2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP
	don't use the DMAMUX IP (instead, channel MUX-ing is performed
	through an eDMA register in the case of i.MX93).

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-01-23 10:54:21 -05:00