Looks like those two SoCs still had old header information depending on
Kconfig from SOF, remove those and set trace size directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Extend the PWM API with optional API functions for capturing PWM pulse
width and period cycles.
Fixes#26026.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Document the use of DEVICE_DT_GET() to fetch device pointers at
compile time, and update the documentation on defining device
instances to use the devicetree macros.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Mark the CANopen sample with program download support as build-only
since it depends on MCUboot being flashed to the board prior to the
generated application firmware image.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
All other silabs_exx32 socs already have this change applied, only
efr32bg13p was missing. This is now done, so all silabs_exx32 are
similar.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
* give user permission to gcov bss section
* expand the size of iccm and dccm to 1M
Signed-off-by: Jingru Wang <jingru@synopsys.com>
Before hooking up the MMU driver code to the Zephyr MMU core code it's
better to match the expected variable types of the two parts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The MMU code is currently assuming that Zephyr only uses one single set
of page tables shared by kernel and user threads. This could possibly be
not longer true in the future when multiple set of page tables can be
present and swapped at run-time.
With this patch a new arm_mmu_ptables struct is introduced that is used
to host a buffer pointing to the memory region containing the page
tables and the helper variables used to manage the page tables. This new
struct is then used by the ARM64 MMU code instead of assuming that the
kernel page tables are the only ones present.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The ARM64 MMU code used to create the page tables is strictly tied to
the custom arm_mmu_region struct. To be able to hook up this code to the
Zephyr MMU APIs we need to make it more generic.
This patch makes the mapping function more generic and creates a new
helper function add_arm_mmu_region() to map the regions defined by the
old arm_mmu_region structs using this new generic function.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
In the current code the base xlat table is a standalone array. This is
done because we know at compile time the size of this table so we can
allocate the correct size and save a bit of memory. All the other xlat
tables are statically allocated in a different array with full size.
With this patch we move all the page tables in one single array,
including the base table. This is probably going to waste a bit of space
but it makes easier to:
- have all the page tables mapped in one single contiguous memory region
instead of having to take care of two different arrays in two
different locations
- duplicate the page tables more quickly if we need to
- use a pre-allocated space to host the page tables
- use a pre-computed set of page tables saved in a contiguous memory
region
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
MESH/NODE/CFG/HBS/BV-01-C expects the MinHops to be 0x7f after
disabling subscription, but 0x00 for subsequent Get requests.
MESH/NODE/CFG/HBS/BV-02-C expects us to return previous
count value and then reset it to 0.
Signed-off-by: Michał Narajowski <michal.narajowski@codecoup.pl>
Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3
is used as a clock source by certain peripherals, e.g. LTDC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Provide a utility function to compute PLL VCO input range so that it
can be re-used for other PLLs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
When flash is Dualbank and flash size is lower than 512K,
then there is a discontinuity between bank1 and bank2.
Also take into account bank swap capability.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When setting baudrate register, baudrate value is computed according
to the oversampling given value, which is default boot time
value (16).
In case oversampling value has been changed by bootloader (as in case
of TFM bootloader), a desynchronsation happens between OVR and BRR
values and the ouptut baudarate is incorrect.
For oversampling register before setting the baudrate to avoid this
situation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Only enable hardware stack protection by default on the NXP TWR-K18F
development board if userspace is not enabled.
The NXP KE1xF SoC has 8 MPU regions, which is insufficient for using HW
stack protection and userspace simultaneously.
Fixes bc9a498bdf.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The #if statement used IS_ENABLED to check if it was defined.
IS_ENABLED will only return true if the value is 1, and false otherwise.
If the NET_TCP_MAX_SEND_WINDOW_SIZE value would be e.g. 8, then the
check would fail.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Make sure that received and out-of-order TCP segments are queued
until we receive proper segments.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If we receive data that is out-of-order, queue sequential
TCP segments until we have received earlier segment or a timeout
happens.
Note that we only queue data sequentially in current version i.e.,
there should be no holes in the queue. For example, if we receive
SEQs 5,4,3,6 and are waiting SEQ 2, the data in segments 3,4,5,6 is
queued (in this order), and then given to application when we receive
SEQ 2. But if we receive SEQs 5,4,3,7 then the SEQ 7 is discarded
because the list would not be sequential as number 6 is be missing.
Fixes#30364
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This is a pairing function with bt_le_scan_cb_register()
to used for remove the scanner callback from callback list.
Signed-off-by: chao an <anchao@xiaomi.com>
When calling irq_rx_ready or irq_tx_ready API, return the logical AND
between the irq status and the enable of that irq.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
"st,mem2mem" property is supposed to be limited to dma-v1.
Remove its use in dma-v2 components.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2 versions of DMA hardware blocks could be found across stm32 series.
In order to simplify the handling of matching Kconfig symbols,
make this visible in dts files by creating "st,stm32-dma-v1" and
"st,stm32-dma-v2" and set them accordingly in dtsi files.
Duplicate and update related bindings to reflect that new state.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adding acrn configurations specific to the platform
on which acrn boots zephyr, Only the EHL specifc
configurations for now. Keeping the HW clock frequency to
1900Mhz for EHL and using the new APIc timer driver.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
LPRAM_BASE and LPRAM_SIZE are duplicates of LP_SRAM_BASE and
LP_SRAM_SIZE respectively. Remove them and use LP_SRAM_*
consistently everywhere.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a
different shim register range, they cannot be accessed, using the
usual SHIM_BASE offset.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
CONFIG_BOOTLOADER_MCUBOOT is never used in cAVS builds, remove
code, supposedly supporting it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
shim.h on cAVS 2.5 contains register definitions, copy-pasted
from other architectures. Fix them to correct values.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
