Commit graph

550 commits

Author SHA1 Message Date
Andy Ross 662b0bf765 drivers/timer: Add x86 APIC TSC_DEADLINE driver
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt.  Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic.  The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default.  Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").

Really this is just ideal for Zephyr.  So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead.  All modern hardware has
what it needs.  The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 16:48:58 -04:00
Aymeric Aillet c5a057bc63 drivers: serial: add Renesas R-Car driver
This patch add support for polling based UART
on the Renesas R-Car SCIF (Serial Communication Interface
with FIFO)

This hardware block can be found on various Renesas R-Car
SoC series.

It allows to get console on R-Car Gen3 H3ULCB board.

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2021-05-07 13:08:48 +02:00
Marcin Niestroj b4854debd1 drivers: wifi: esp_at: rename driver from esp
Recently WiFi ESP32 driver (utilizing WiFi radio in ESP32 SoC) was
introduced into drivers/wifi/esp32/ and it already caused confusion as
there was existing drivers/wifi/esp/ directory for ESP-AT
driver (utilizing external WiFi chip, by communicating using AT commands
from any serial capable platform). So question has arisen whether it is
good to merge both, while they are totally different drivers.

Rename ESP-AT driver to be placed in drivers/wifi/esp_at/, so that it is
easier to figure out difference between "esp32" and "esp_at" just by
looking at driver name. Rename also DT compatible and all Kconfig
options for the same reason.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-05-06 13:21:39 -04:00
Gerard Marull-Paretas 605a3d1a8a samples: pm: move to pm folder
Adjust naming to make things more consistent.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-05-05 18:35:49 -04:00
Gerard Marull-Paretas 99cbee3f16 pm: move power subsystem to pm
Adjust naming to make things consistent.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-05-05 18:35:49 -04:00
Gerard Marull-Paretas 25bb163dc2 pm: reorganize headers
- Move PM related APIs to `include/pm` so that it follows API `pm_`
  prefix namespace. In order to make transition easier
  `include/power/power.h` is kept pointing to `include/pm/pm.h`.
- Move most of device PM related content from `include/device.h` to
  `include/pm/device.h` and `include/pm/runtime.h`.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-05-05 18:35:49 -04:00
Kalyan Sriram cf6a7f3ca6 codeowners: add code owner for blackpill_f401ce, blackpill_f411ce
Add @coderkalyan (Kalyan Sriram <coder.kalyan@gmail.com>) as code owner
for blackpill_f401ce, blackpill_f411ce boards.

Signed-off-by: Kalyan Sriram <kalyan@coderkalyan.com>
2021-04-30 12:40:24 -05:00
Daniel Leung a5ab1a7518 logging: add support for dictionary based logging
This adds dictionary based logging support. Dictionary based
logging is binary based where one big difference is that
static strings are stored as pointers instead of the whole
string. This results in reduced space requirements for
storing log messages in certain scenairos.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-04-28 22:25:42 +02:00
Daniel Leung 1117169980 kernel: generate placeholders for kobj tables before final build
Due to the use of gperf to generate hash table for kobjects,
the addresses of these kobjects cannot change during the last
few phases of linking (especially between zephyr_prebuilt.elf
and zephyr.elf). Because of this, the gperf generated data
needs to be placed at the end of memory to avoid pushing symbols
around in memory. This prevents moving these generated blocks
to earlier sections, for example, pinned data section needed
for demand paging. So create placeholders for use in
intermediate linking to reserve space for these generated blocks.
Due to uncertainty on the size of these blocks, more space is
being reserved which could result in wasted space. Though, this
retains the use of hash table for faster lookup.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-04-27 13:32:00 -04:00
Carlo Caione 0427d93f4a board: arm64: Add FVP Base RevC 2xAEMv8A board
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).

INFO    - Total complete:  256/ 256  100%  skipped:  933, failed:    0

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-27 13:30:07 -04:00
Erwan Gouriou 45418dedc0 CODEOWNERS: Add code owner for dts/common
Add @galak as codeowner for dts/common


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-27 11:53:37 +02:00
Kumar Gala e1032ad2c3 include: Move emul.h to drivers/emul.h
Move emul.h out of the top level include/ dir into
include/drivers/emul.h and deprecated the old location.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-04-22 12:51:01 -04:00
Jiafei Pan 6f46a92849 board: nxp_ls1046ardb: add 2 cores smp for running in Jailhouse
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
   inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
   run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
   dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-22 11:29:54 +02:00
Julien Massot d86c61fd57 drivers: gpio: add Renesas RCar gpio
Add GPIO controller driver that can be found on Renesas
RCar gen3 soc series.

Controller can handle up to 32 GPIOs per banks.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Julien Massot 20fdb6cbfb drivers: timer: add R-Car cmt driver
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Julien Massot 2ad6e4e376 drivers: clock_control: add R-Car CPG MSSR driver
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.

MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.

CPG registers allow to get the rate or to set some divider like for
the CAN clock.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Julien Massot b21a0d0116 boards: arm: Add support for R-Car H3ULCB board
Add basic configuration for H3ULCB, just enough to see the
Zephyr boot banner on the ram console.

This configuration make use of the Cortex-R7 present on
r8a977951 SoC.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Julien Massot dc26d6bb4a soc: arm: add Renesas rcar_gen3 series support
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.

- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2

Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).

This first SoC definition is just enough to print Hello World in a
ram console.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Anas Nashif f63c9b1893 codeowner: path updates
path updates after moving directories.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-04-20 08:45:05 -04:00
Guillaume Paquet d3d789d7ee boards: arm: Add RAK4631 Wisblock Core LPWAN board
Add rak4631 board from RAKWireless based on nrf52840 and SX1262.
Board Documentation is completed

Signed-off-by: Guillaume Paquet <guillaume.paquet@smile.fr>
2021-04-19 11:01:24 -04:00
Jaxson Han 985b03340d board: arm64: Add FVP BaseR AEMv8R board
Add essential files to create a new board. Enable arch timer, uart,
multi-threading. Set memory map for flash and sram. The new board name
is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jaxson Han 30ed92c218 arch: arm64: Armv8-R AArch64 MPU implementation
Armv8-R AArch64 MPU can support a maximum 16 memory regions, and the
actual region number can be retrieved from the system register(MPUIR)
during MPU initialization.
Current MPU driver only suppots EL1.

Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jaxson Han 475374ce2f include: arm64: Add mpu data struct definition
According to Armv8-R64 Spec, MPU related meta data(region base/limit)
is 64 bits. So we need to re-define MPU related data structure here.

Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jaxson Han 8f46bc97a3 dts: arm64: Add dtsi and dts binding for cortex-R82
Add armv8-r dtsi.
Add dts binding yaml file for cortex-R82.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jaxson Han ade060ed1f soc: arm64: Add FVP AEMv8R AArch64 soc
Add essential files to create a new soc.
Introduce a new type of soc series named fvp_aemv8r.
Add a new soc named fvp_aemv8r_aarch64.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jiafei Pan 865c81889d CODEOWNERS: add myself as Layerscape code-owner
Add myself to be NXP Layserscape SoC and LS1046A board
code-owner.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-09 13:25:15 +02:00
Gerard Marull-Paretas 89c8a4f09e known-issues: delete out of date content
It turns out that current known issues folder contains issues that are
no longer valid or present. I have searched for some of the regex
snippets listed but I have not been able to find any. Documentation was
the last active user of the known-issues folder, but has moved to
another solution.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-04-08 09:55:16 +02:00
Sun Amar 252f1b8e0d gecko pwm: add pwm driver for the gecko.
pwm driver + Kconfig and Cmake files for the
efr32 soc family.

Signed-off-by: Sun Amar <sun681@gmail.com>
2021-04-02 18:45:33 -04:00
Carlo Caione a43f3bade8 arm/arm64: Fix misc and trivials for ARM/ARM64 split
Fix the header guards, comments, github labeler, CODEOWNERS and
MAINTAINERS files.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-31 10:34:33 -05:00
Lukasz Majewski a1c0821b46 arm: Add code owner for the Segger's ip_k66f board
I would like to add myself as a co-maintainer for the ip_k66f
board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2021-03-31 10:26:44 -05:00
Maureen Helm cdd2c451f0 MAINTAINERS: CODEOWNERS: Add NXP collaborators
Add @mmahadevan108 and @dleach02 as collaborators for NXP SoCs, boards,
and drivers.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-03-31 07:51:26 -04:00
Gerard Marull-Paretas 3282cf8ef2 doc: move scripts to _scripts
Move Sphinx related content to folders with underscore prefix.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-03-31 10:39:48 +02:00
Kumar Gala 0bb4665df7 include: Move ptp_clock.h to drivers/ptp_clock.h
Move ptp_clock.h out of the top level include/ dir into
include/drivers/ptp_clock.h and deprecated the old location.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-25 10:09:33 +02:00
Kumar Gala 95e4b3eb2c arch: arm: Add initial support for Cortex-M55 Core
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).

The support is based on the Cortex-M33 support that already exists in
Zephyr.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-23 13:13:32 -05:00
Johann Fischer ae7097ddd9 CODEOWNERS: add myself as disk subsystem code-owner
Add myself as disk subsystem code-owner

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-03-23 12:16:01 +01:00
Johann Fischer 69a5f07d16 drivers: disk: cleanup after driver relocation
Add common SDMMC_LOG_LEVEL and SDMMC_VOLUME_NAME.
Initialize drivers at POST_KERNEL level.
Update CODEOWNERS after sdmmc drivers relocation.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-03-23 12:16:01 +01:00
Eugeniy Paltsev 11aedbc460 CODEOWNERS: Add evgeniy-paltsev as an ARC part owner
Add @evgeniy-paltsev as an ARC part owner in addition to
@abrodkin and @ruuddw, so he will be chosen as a reviewer
automatically.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2021-03-22 15:46:51 -04:00
Hubert Miś 7d8f78a08b drv: display: Initial FT800 display driver
This patch includes initial support for FT800 display driver.
It includes basic features. It can be easily extended with more
FT800 display list and co-processor features.

Signed-off-by: Hubert Miś <hubert.mis@gmail.com>
2021-03-19 19:05:53 +01:00
Johann Fischer 46f53332f8 CODEOWNERS: add codeowner for modbus
Add myself as codeowner for modbus subsys.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-03-19 15:50:21 +01:00
Dean Weiten 5e82563601 board: arm: ronoth_lodev: add Ronoth LoDev board support
The Ronoth LoDev in an open source board which uses
the AcSIP S76S.

Signed-off-by: Dean Weiten <dmw@weiten.com>
2021-03-18 08:48:30 -05:00
Dean Weiten ed1b220ba5 dts: arm: s76s: add AcSIP S76S SiP support
The AcSIP S76S is a STM32L073+SX1276+PA SoC which
supports LoRa communications.

Signed-off-by: Dean Weiten <dmw@weiten.com>
2021-03-18 08:48:30 -05:00
Peter A. Bigot 16f4a47694 CODEOWNERS: remove my assignments
I won't be supporting Zephyr for the foreseeable future, so remove my
association with specific subsystems.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2021-03-18 06:16:23 -04:00
Yonatan Schachter 1d9f0e35a9 soc: silabs_exx32: Add support for EFR32FG13P SoC
This commit adds support for Silicon Labs EFR32FG13P (Flex Gecko) SoC.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2021-03-17 19:33:35 -05:00
Gerson Fernando Budke 68dcac3be6 dts: arm: cypress: Introduce PSoC-6 pinctrl
Introduce PSoC-6 pinctrl infraestructure and definitions.  This add
files to handle devicetree entries and following modifications:

 - add pinctrl bindings
 - update gpio bindings with pin-cells
 - add pinctrl node and move gpio nodes inside
 - declare pinctrl for current uart entries

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-03-16 13:36:15 -05:00
Martin Jäger 1aaf508bde task_wdt: add task-level watchdog subsystem
This new subsystem can be used to supervise individual threads. It
is based on a regularly updated kernel timer, whose ISR is never
actually called in regular system operation.

An existing hardware watchdog can be used as an optional fallback if
the task watchdog itself gets stuck.

Signed-off-by: Martin Jäger <martin@libre.solar>
2021-03-15 12:24:54 +01:00
Wojciech Tatarski 35dd66b6c4 drivers: gpio: add EOS S3 GPIO driver
Add GPIO driver for QuickLogic EOS S3 SoC.

Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>

Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-03-11 08:58:20 -05:00
Anas Nashif 7567f232cc CODEOWNERS: update file path for samples
Adapt to new location of samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-09 17:48:18 -05:00
Andrei Emeltchenko 17cd6fe90d MAINTAINERS: Remove myself as a USB maintainer
I have not had time to work with USB recently, so removing myself from
MAINTAINERS and CODEOWNERS for the USB subsystem.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-03-08 10:06:11 -05:00
Nicolas Pitre 14e5e98822 lib: cbprintf: add support for deferred formatting
In applications like logging the call site where arguments to
formatting are available may not be suitable for performing the
formatting, e.g. when the output operation can sleep.  Add API that
supports capturing data that may be transient into a buffer that can
be saved, and API that then produces the output later using the
packaged arguments.

[ Documentation and commit log from Peter Bigot. ]

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-03-05 09:29:35 +01:00
Asbjørn Sæbø 66f699b8ea Bluetooth: Audio: Add maintainers/codeowners
Add Thalley (emil.gydesen@nordicsemi.no) and asbjornsabo
(asbjorn.sabo@nordicsemi.no) as additional maintainers/codeowners for
bluetooth audio.

(Also adds empty audio.h file, that will later be expanded, so that
the include/bluetooth/audio directory now listed in CODEOWNERS
actually exists.)

Signed-off-by: Asbjørn Sæbø <asbjorn.sabo@nordicsemi.no>
2021-03-04 18:00:35 -05:00