Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
llvm will generate a different div instruction than gcc does and than
the number of types that the div instruction opcode takes is not 2.
Move to using inline asm with a idivl instruction to ensure the opcode
size is what we expect so that exc_divide_error_handler() can properly
skip over the instruction.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
The RISC-V FPU context switching code is intricate and sometimes subtle.
Here's a test that exercizes various code paths to ensure they work as
intended, and to confirm that the target hardware does behave as
expected too.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add another clause in the test_ram_perms code to verify that any pinned
regions have the correct flags.
Signed-off-by: Keith Packard <keithp@keithp.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all thruthy errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(truthy)'
This only accepts true/false for boolean properties. Seems like python
takes all sort of formats:
https://github.com/yaml/pyyaml/blob/master/lib/yaml/constructor.py#L224-L235
But the current specs only mention "true" or "false"
https://yaml.org/spec/1.2.2/#10212-boolean
Which is the standard yamllint config.
Excluding codeconv and workflow files, as some are using yes/no instead
in the respective documentation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
integration_platforms help us control what get built/executed in CI and
for each PR submitted. They do not filter out platforms, instead they
just minimize the amount of builds/testing for a particular
tests/sample.
Tests still run on all supported platforms when not in integration mode.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Picolibc uses the libc partition for some variables, so make sure
the test allows references to that data.
Signed-off-by: Keith Packard <keithp@keithp.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
For tests that set CONFIG_MP_NUM_CPUS, switch to using
CONFIG_MP_MAX_NUM_CPUS instead as we work to phase out
CONFIG_MP_NUM_CPUS.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
The thread swap test was making use of a register to point to
ztest_thread_callee_saved_regs_container, which was being clobbered
in the inline assembly code, causing a hard-fault in certain cases.
This commit adds a clobber list of the registers used, causing the
compiler to assign ztest_thread_callee_saved_regs_container to an
appropriate (unclobbered) register.
It also addresses an issue in the v6-m and v8-m.baseline inline
assembler where only 4 of the 8 callee-saved registers were being
set from ztest_thread_callee_saved_regs_container, due to a double
use of `ldmia` on the same four registers. Since v6-m devices can't
operate outside r0-r7 on most instructions, the upper 4 callee-saved
registers are set first with `ldmia`, before setting the lower 4.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
The current stm32l562_dk_ns has no flash partitions defined. This add
flash partitions following partition sizes that are compatible with
the TF-M platform defined at flash_layout.h and removes the redundant
overlays board files.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
... and tests are built with no optimizations. The standard size may
not be sufficient in such circumstances.
Commit 4b1103547c addressed the same
issue in a single test and used a higher value (1024) that turns out
to be not necessary, so revert also that change to make the cleanup
easier when the workaround will no longer be needed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Convert the device to be Devicetree based. Adjusted tests and other
areas that were using old Kconfig properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The "framebuf" driver was an incomplete driver expecting _clients_ to
implement missing functionality (i.e. init and device definition)
outside of the driver. This pattern of scattering driver code throughout
the tree is not common (if used at all). If certain drivers share
functionality, one can create a common module within the subsystem (see
e.g. ILI9XXX drivers).
The _generic_ framebuffer code was only used to implement the Intel
Multiboot framebuffer driver. This patch centralizes all the scattered
code in the subsystem and adjusts the driver name to "intel_multibootfb"
to make things clear. If there's ever another framebuffer driver that
shares code, it can be split into multiple modules.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Simple tests to check the sanity of implementations. As with any tests
involving time, a constant "tolerance" of 10% is used in some of the
measurements.
Checks are basically answering the questions 1) "is time always
increasing?" and 2) "at a somewhat constant pace?". And some tests for
the time conversion, answering "is the elapsed time in nanoseconds
somewhat coherent?".
As timing and emulation are a somewhat dangerous combination,
`testcase.yaml` exclude CONFIG_QEMU_TARGET=y from tests.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Increase stack size for test thread. With no optimization
default stack size may not be enough.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit enables the assert test mode (`CONFIG_ASSERT_TEST`) for the
ARM interrupt test because it relies on the assert function to return
without aborting in the "Assert occurring inside kernel panic" test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit enables the assert test mode (`CONFIG_ASSERT_TEST`) for the
ARM interrupt test because it relies on the assert function to return
without aborting in the in-ISR "Intentional assert" test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
If the test is run with the config NO_OPTIMIZATIONS enabled then the
stack size usage increases by around 80% for ARM platforms.
Increase the stack size used in test cases that enables building with no
optimizations for ARM.
Update description on TEST_ARM_CORTEX_M since it was outdated and said
it was only used for a single purpose.
Fixes: #47930Fixes: #47929Fixes: #47855
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The test fails on several stm32 platforms, due to the
correlation between test_arm_syscalls and
test_arm_thread_swap, so disable the corresponding IRQ
interrupt may fix it.
Signed-off-by: Shaoan Li <shaoanx.li@intel.com>
This test has been bitrotting for a while - years, in fact. As it didn't
have a `testcase.yaml`, it wasn't being run on twister. The code expects
to be run on single thread environment, but xtensa arch currently
doesn't support that.
This patch simply removes this test - if it's deemed important, it can
be reworked and readded in the future.
Fixes#47508.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Move the direct interrupt test to tests/arch/x86/direct_isr. Two
reasons:
1. The direct interrupt is only for x86. It's arch-specific.
2. And it need extra gcc option to pass the build, that will
include testsuite number. Although it seems like we add a
extra testsuite for it, actually we can reduce whole tests
configuration in tests/kernel/interrupt. And also make this
test more generic as it used to be.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Following implementation of commit 219d5b5,
and to complement commit 8c4f98d
it is also necessary define _vector_end in
test specific arm-irq-vector-table.ld
Fixes#47273
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Disabling nucleo_l552ze_q_ns from the test suite since there isn't
enough room to sign the image with the toolchain used in CI. This can
be reverted if changes are made to the nucleo_l552ze_q_ns platform to
enable enough room for the signing data.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
