Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This rework module hal_gigadevice to be compliance with rule
that requires firmware libraries directories names be lowercase.
This rule was created at hal_gigadevice/README and it is not
a Zephyr general rule. This only affect how hal_gigadevice is
used.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
GD32F4XX requires access to SoC definitions (e.g. GD32F450) when
including library header files, so expose them at Zephyr level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This add access to modules/hal/gigadevice with three firmware
libraries by updating west.yaml file:
- GD32E10X ARM (Cortex-M4F)
- GD32F403 ARM (Cortex-M4F)
- GD32VF103 RISC-V (Nucleisys Bumblebee core)
It introduce module/hal_gigadevice, which contains all Cmake
and Kconfig rules to build GigaDevice SoCs into zephyr main
tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
