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798 commits

Author SHA1 Message Date
Francois Ramu 62e7b788aa drivers: timer: stm32 lptimer when sleeping for -1
When CONFIG_SYSTEM_SLOPPY_IDLE is not set, then system
can sleep for -1 means waking Up at the max possible
counter value (INT_MAX)
When CONFIG_SYSTEM_SLOPPY_IDLE is set sleeping K_TICKS_FOREVER
means never wakingUp

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-02-26 11:48:22 +01:00
Andrzej Głąbek bb065262bc drivers: timer: nrf_grtc_timer: Add dependency on nRF clock control
... in the related parts, so that the driver can be used on nRF54H20
where the clock control is not present yet.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-02-02 16:40:11 +01:00
Andrzej Głąbek 139b97a64a modules: hal_nordic: Use common nrfx_config section for GRTC
Move code that prepares `NRFX_CONFIG_GRTC_*` definitions based on
information from devicetree from the nRF54L15 nrfx_config header
to the global one, so that the code can be used by nRF54H20, too.

The checks that validate owned-channels and child-owned-channels
DT properties are moved to the nrf_grtc_timer driver so that
the global nrfx_config is not polluted unnecessarily.

The default values in nrfx_config_nrf54l15_enga_application.h
are restored to those from the corresponding template file.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-02-02 16:40:11 +01:00
Dino Li a059da947c soc/it8xxx2: add support for raising EC bus to 24MHz
This change was made to reduce read/write EC registers latency.
Without enabling CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ:
- Read EC register 64 times takes 80us latency.
- Write EC register 64 times takes 60us latency.
With enabling CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ:
- Read EC register 64 times takes 40us latency.
- Write EC register 64 times takes 30us latency.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2024-01-31 16:43:46 +00:00
Magdalena Pastula b605c4219b drivers: timer: add GRTC driver
Add Nordic driver for GRTC.

Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
2024-01-30 21:00:44 +00:00
Witold Lukasik ae78cf017d drivers: timer: move SYSTEM_CLOCK_WAIT to Kconfig.nrf_xrtc
SYSTEM_CLOCK_WAIT will be a common part for a next
version of Nordic timer.

Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
2024-01-30 21:00:44 +00:00
Guillaume Gautier 58c296b30f drivers: timer: stm32 lptim: add support for backup standby timer
Add support for a backup standby timer in STM32 LPTIM driver for cases
when the LPTIM is not available (ie standby low power mode).
A counter (typically RTC) is used for such a case.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-01-25 08:55:02 +01:00
Guillaume Gautier e541666d90 drivers: timer: stm32: lptim: remove init to 0 of static
Remove initialization of static variable to 0 to prevent resetting the
value when reinitializing the driver after resume from standby.
This has no impact since static variables are initialized to 0 by default.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-01-25 08:55:02 +01:00
Gerard Marull-Paretas a63591c5cb drivers: timer: litex: add missing include
<soc.h> is needed to access IO R/W functions like litex_read8.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-19 15:13:53 +00:00
Erwan Gouriou 0a2876de26 drivers: timer: stm32: Clean up related to STM32_LPTIM_CLOCK
Now that STM32_LPTIM_CLOCK choice symbol is defined from device tree,
remove the prompt which was defining it as a user selectable entry.

Remove the warning related to possible symbol misalignment with
device tree setting.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-01-16 10:07:02 +00:00
Bryan Zhu a417392f76 timer: ambiq_stimer: Correct set_timeout's delta clock calculation
In sys_clock_set_timeout(), input "ticks" is used to compute next
timeout point, Ambiq's STimer API used to sets next timeout has input
parameter as ui32Delta, which inside the API is using
"this value to add to the STimer counter and load into the comparator
register" according to its spec, thus the this delta clock is
almost equivalent to input "ticks"'s concept, and is not related to
last_count, it should be computed directly from input "ticks".
This correction fixes the test case failure at
zephyr\tests\kernel\tickless\tickless_concept.

Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
2024-01-08 10:07:46 +01:00
Bryan Zhu 67099d2bba timer: ambiq_stimer: fixing disabling tickless not working issue
In init function, start timer with period CYC_PER_TICK if tickless is
not enabled, This change is for fixing the issue that disabling
CONFIG_TICKLESS_KERNEL the OS tick is not work issue, this
causes the OS not starting scheduling correctly.

Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
2023-12-18 15:03:35 +01:00
Marek Vedral 6068255512 drivers/timer/arm_arch_timer: Fix cycles overflow with GDB stub
If GDBSTUB is enabled and the kernel runs in tickless mode, the timer
must not convert the delta cycles to a 32-bit data type (cycle_diff_t in
this case). The delta_ticks variable would overflow and the next timeout
would be set before the current timestamp, thus generating an interrupt
right after leaving the handler. As a result, the system would receive
tens of thousands of interrupts per second and would not boot.

Cc: Michal Sojka <michal.sojka@cvut.cz>
Signed-off-by: Marek Vedral <marek.vedral@gmail.com>
2023-12-18 09:31:42 +01:00
Adam Wojasinski b7949766e6 drivers: timer: nrf_rtc_timer: Change HAL to HALY in RTC timer driver
NRFX has introduced HALY software layer which is a superset of HAL
and aggregates some hardware registers manipulations in a single
function calls.

Quote from nrfx changelog:

"HALY is an extension of the HAL layer that aggregates basic hardware
use cases within single functions. Now it is used instead of HAL
in the corresponding drivers."

This commit zephyr's driver to be aligned with the approach used
in nrfx, where drivers has been switched to use HALY instead of HAL.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2023-12-14 09:28:15 +01:00
Francois Ramu eeb7a88ff0 drivers: timer: stm32 lptimer adjust the TICKS_PER_SEC to LPTIM clock
With low LPTIM freq when prescaler is set to 16 or 32,
the CONFIG_SYS_CLOCK_TICKS_PER_SEC must be reduced to
LPTIM CLOCK_/prescaler to avoid spurious timer wakeup activity.
Assert error if the CONFIG_SYS_CLOCK_TICKS_PER_SEC
is not compatible with the lptim clock freq.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-12-12 09:52:30 +00:00
Francois Ramu a19eb7cf88 drivers: timer: stm32 lptimer clock prescaler property
Rename to LPTIM_PRESCALER, the <st,property> prescaler of
the stm32 LPTimer. This commit gives better readability than
LPTIM_CLOCK_RATIO.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-12-12 09:52:30 +00:00
Alberto Escolar Piedras 9f15c41a7e drivers/timer native: Replace native_posix with native_posix/sim
This driver is applicable to both targets.
Let's be clear about that.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-12-07 10:39:31 +00:00
Dawid Niedzwiecki 75f7ffb2c9 Revert "timer: cortex_m_systick: handle cycle count overflow with idle timer"
This reverts commit 2ae09993ca.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-30 10:05:22 +01:00
Dawid Niedzwiecki 733bddb32e timer: cortex_m_systick: idle timer: handle no sleep case
SysTick usually has higher measurement resolution than the IDLE timer.
When the time in low power mode is very short or 0, it is possible that
SysTick usually has measures more time since the sys_clock_set_timeout
than the idle timer.

Handle that case to keep uptime correct.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-27 19:58:23 +01:00
Dawid Niedzwiecki 4104f54987 timer: cortex_m_systick: handle idle timer overflow
The idle timer has its max value and can overflow. We measure time passed
since the sys_clock_set_timeout call. Take possibility of the overflow
into account.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-27 19:58:23 +01:00
Dawid Niedzwiecki 2ae09993ca timer: cortex_m_systick: handle cycle count overflow with idle timer
When the idle timer is in use, we calculate number of cycles passed
since the sys_clock_set_timeout call.

The cycle counter can overflow easily, when the counter is 32-bit wide.
Handle that case.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-27 19:58:23 +01:00
Francois Ramu f1af7f13eb drivers: timer: stm32 lptimer revert static-prescaler
Revert "drivers: timer: lptim timer clock on stm32u5 has a prescaler"
This reverts commit c14670abea.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-11-27 12:18:41 +00:00
Dawid Niedzwiecki a877bb5001 timer: cortex_m_systick: add idle timer dependency
Allow enabling the Cortex-m idle timer only if power management is set.
It doesn't make sense to use an idle timer without PM.

It allows adding the idle timer chosen node to dts without enabling the
idle timer by default. Now, the PM config has to be set as well.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-22 09:28:53 +00:00
Jun Lin 4cfd4b5379 driver: timer: npcx: fix announce/set timer timeout tick
The timer driver doesn't annouce/set the timeout at the tick boundary
but at the absolute next expiration time.
It will cause the accumatlation of the tick drift and cannot pass the
kernel/timer/timer_behavior test suite.
This commit fixes the tick drift problem by annouce the time at the tick
bouandry.

Fixes #59594

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-11-17 17:24:14 +00:00
Dawid Niedzwiecki 457d437841 timer: cortex-m systick: add idle timer
Some chips, that use Cortex-M SysTick as the system timer, disable a
clock in a low power mode, that is the input for the SysTick e.g.
STM32Fx family.

It blocks enabling power management for these chips. The wake-up
function doesn't work and the time measurement is lost.

Add an additional IDLE timer that handles these functionality when the
system is about to enter IDLE. It has to wake up the chip and update the
cycle counter by time not measured by the SysTick. The IDLE timer has to
support counter API (setting alarm and reading current value).

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-07 09:42:37 +01:00
Andrei Emeltchenko 4e946262cb boards: ish: Continue to use HPET_TIMER for ISH and Qemu
Fot Qemu and intel_ish boards continue to use HPET_TIMER.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-10-23 10:34:03 +02:00
Andrei Emeltchenko d6035f4a26 drivers: timer: Select APIC_TSC_DEADLINE_TIMER by default
Select APIC_TSC_DEADLINE_TIMER as default timer for x86.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-10-23 10:34:03 +02:00
Andrei Emeltchenko 19e32dc31e drivers: timer: Refactor x86 system timer selection
Refactor timer selection to allow to select only one timer.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-10-23 10:34:03 +02:00
Alberto Escolar Piedras 7e852d1708 drivers timer nrf: Correct dependencies for simulation
Let's make the nrf rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets
so the configuration matches in both cases.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-10-20 15:14:30 +02:00
Grant Ramsay 236318332b drivers: systick: Fix Cortex-M SysTick dropping 1 cycle per tick
`last_load` is the full N cycles and `SysTick->LOAD` should
be loaded with `last_load - 1` for the calculations work
correctly.

Note: This only affects a kernel in ticked operation.
Tickless kernels periodically restart the timer correctly.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-10-05 15:30:20 +01:00
Grant Ramsay e032f9520d drivers: systick: Fix Cortex-M systick jumping forward and back again
The existing implementation did not properly
handle when `SysTick->VAL` is zero.

This caused three subtle edge cases:
* val1=0,COUNTFLAG=0,val2=0
  This should result in no cycles elapsed,
  however `(last_load - val2) = last_load`.
  So an extra `last_load` cycles was returned.
* val1=0,COUNTFLAG=0,val2=(last_load-1)
  This should result in 1 cycle elapsed,
  however `val1 < val2` so an extra `last_load`
  cycles was returned.
* val1=[2,1,0],COUNTFLAG=1,val2=0
  This should result in `last_load` cycles elapsed.
  However, `last_load * 2` cycles was returned.

To fix the calculation, val1 and val2 are first
wrapped/realigned from [0:last_load-1] to [1:last_load].

Tidy comments to better reflect the SysTick
behaviour and link reference manuals.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-10-05 15:30:20 +01:00
Andrzej Kuros d44e96e486 nrf53: pretick with NRF_802154_RADIO_DRIVER
The `SOC_NRF53_RTC_PRETICK` option is now allowed to be used with
`NRF_802154_RADIO_DRIVER`.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Andrzej Kuros e03d5d4c6d nrf53: RTC pretick allows user channels and require just one CC
The nrf53 pretick can be used with non-zero
`NRF_RTC_TIMER_USER_CHAN_COUNT` Kconfig option.

The nrf53 pretick requires just one RTC1 CC channel.

The nrf53 pretick handles also RTC1 and RTC0 both CCs and OVERFLOW
events by examination of events scheduled on them. The pretick is set
based on number of ticks to the closest event scheduled that can trigger
an interrupt.

Because the operation in `z_arm_on_enter_cpu_idle` hook would
take too much time with interrupts disabled, the
`z_arm_on_enter_cpu_idle_prepare` hook enabled by Kconfig option
`ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK` is used. It performs RTC0 and RTC1
examination, and sets pretick without interrupts being blocked.

The LDREX/STREX are leveraged to detect if exception took place
between start of `z_arm_on_enter_cpu_idle_prepare` and
`z_arm_on_enter_cpu_idle`. If exception has not been taken, the pretick
calculation can be trusted because source data could not changed and
too much time could not pass. Otherwise the sleep attempt is disallowed,
the idle will loop again and try later.

Prompt for `SOC_NRF53_RTC_PRETICK` Kconfig option allows to control
this option by an user and turn the feature off if necessary.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Krzysztof Chruściński 31eaffdf05 nrf53: Add RTC pretick
Add RTC pretick option that triggers HW activity one tick before and
RTC event that leads to the interrupt. Option is active only on nrf53
network core.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2023-09-30 18:48:19 +02:00
Gerard Marull-Paretas 691facc20f include: always use <> for Zephyr includes
Double quotes "" should only be used for local headers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-14 13:49:58 +02:00
Gerard Marull-Paretas 12b2ee54e3 drivers: timer: s/device.h/init.h
Timer "drivers" do not use the device model infrastructure, they are
singletons with a SYS_INIT call. This means they do not have to include
device.h but init.h. Things worked because device.h includes init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-29 11:29:18 +01:00
Gerard Marull-Paretas 9c961571a2 modules: cmsis: move glue code to modules/cmsis
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).

To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.

All files including CMSIS have been updated.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Maciej Sobkowski 5ffce32376 drivers: timer: Add driver for Ambiq system timer (STIMER)
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.

Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Marek Matej 6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
Francois Ramu 6254527343 drivers: timer: stm32 lptim driver check clock_control_on return code
This PR is Calling "clock_control_on" and checking return value
(as is done elsewhere 10 out of 11 times)
CID 322066:  Error handling issues  (CHECKED_RETURN)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-07-19 10:14:30 +00:00
Erwan Gouriou 3359259a69 drivers: timers: Add LPTIM support for STM32WBA
Add LPTIM support for STM32WBA

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-07-12 11:48:10 +02:00
Florian Grandel 75c83edc48 dts: ti: cc13xx_cc26xx: devicetree sysclk alignment
This change introduces the "_rtc_timer" suffix for the system tick timer
driver "compatible" property and aligns naming conventions with the
actual CC13/26xx SoC series product policy.

This frees up the "_rtc" namespace to introduce additional APIs based on
the same peripheral in the future (not part of this PR):

rtc: rtc@... {
  compatible = "ti,cc13xx-cc26xx-rtc";
  ...

  timer {
    compatible = "ti,cc13xx-cc26xx-rtc-timer";
    ...
  };

  counter {
    compatible = "ti,cc13xx-cc26xx-rtc-counter";
    ...
  };

  pps {
    compatible = "ti,cc13xx-cc26xx-rtc-pps";
    ...
  };
};

Or alternatively an MFD pattern with similar requirements.

Fixing the namespacing now makes sense standalone as it reduces the
chance of custom drivers being broken in the future.

Redundant extension of the mandatory system clock devicetree node is
replaced with a single `status = "okay"` which seems to be the more
sensible default to avoid user error when defining custom boards.
Knowledgeable users can still override this if really needed.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-07 18:46:24 -04:00
Florian Grandel 38e2eb8fe6 soc: ti: cc13/26xx: clean up include hierarchy
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-07 18:46:24 -04:00
Nicolas Pitre 49580bd374 drivers: systick: implement option for sys_clock_cycle_get_64()
This driver, due to its limited 24-bits counter, is already tracking a
cycle count in software. Allow that count to be a 64-bits value so this
won't wrap in a matter of only a few seconds when the hardware clock
is fast.

This is very cheap to do as expensive math operations (i.e. divisions)
are performed only on counter intervals whose values fit in 32 bits like
before.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-07-01 12:04:10 +02:00
Alexander Razinkov cb491cacad drivers: support 64-bit addresses from devicetree for PLIC, MTIMER, UART
Usage of 64-bit address constants from devicetree without
an UINT64_C wrapping macro results in the following warning
and the cut-off of the address value:

"warning: integer constant is so large that it is unsigned"

This change fixes such issue for PLIC, MTIMER and UART in case
they are used with some 64-bit RISC-V platforms

Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
2023-06-25 03:29:54 -04:00
Andrey Borisovich 7595cafb02 intel_adsp: timer: implemented sys_clock_idle_exit function
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrzej Kuros a6615ac11f drivers: timer: add z_nrf_rtc_timer_exact_set
The function `z_nrf_rtc_timer_exact_set` is added to allow
setting compare channel without possible creeping of cc val.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-06-19 08:53:06 +02:00
Nicolas Pitre df6084fec1 riscv_machine_timer: remove unused config option
This should have been removed in commit 11a2107d99 ("riscv: timer:
driver revamp").

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-06-01 04:53:19 -04:00
Roman Dobrodii defb159ab1 soc/arm/silabs: support BLE with PM in Series 2 SoCs
Using EM2 or deeper sleep states (where HF clocks are off) requires
special care if BLE radio is used, since BLE radio relies on that clock,
and its power/clock requirements need to be taken into account
On SiLabs, radio PM is implemented as part of RAIL blob, which relies
on sl_power_manager HAL service. I've implemented SoC PM
state changes using sl_power_manager instead of emlib, and added
call to RAIL PM initialization in Gecko HCI driver.

Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
2023-05-24 13:31:44 -04:00
Roman Dobrodii 549358255f drivers/timer/gecko_burtc: allow queries prior to timer initialization
Before BURTC is initialized, clock to its APB CSR file is stopped, so
any attempt to read BURTC regs results in BusFault. However,
many parts of Zephyr may call sys_clock getters even before sys_clock
driver itself is initialized. This change adds support for that:
sys_clock_elapsed() and sys_clock_cycle_get_32() simply return 0
if BURTC is not init yet.

Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
2023-05-24 13:31:44 -04:00