This commit adds PWM LEDs to the boards DTS. This was
verified by running the pwm_leds example.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
An application with the following config fails to link on nrf53 app
core:
```
CONFIG_BT=y
CONFIG_BT_HCI_RAW=y
CONFIG_ENTROPY_GENERATOR=y
```
This happens because `entropy_bt_hci.c` uses functions from
`hci_core.c`, which is only compiled if `BT_HCI_HOST` is selected.
Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
STM32WB55xG MCUs include 256 KiB of SRAM split into three banks.
The size of the main bank is 192 KiB, and not 96 KiB as it was
specified in the device tree. This commit fixes the issue and
also updates the definition of the NUCLEO-WB55 board, based on
a STM32WB55RG MCU.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Add the PWM period cell to PWM driven LEDs. A value of 20 msec has been
chosen as it is the most common value used in other boards.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Updated all PWM specs to include the period cell. Because all specs
refer to PWM driven LEDs, a period of 20 msec has been chosen, as most
other platforms do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Updated all PWM specs to include the period cell. Because all specs
refer to PWM driven LEDs, a period of 20 msec has been chosen, as most
other platforms do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period was set to 0, a value not meaningful to drive an LED. A value
of 20 msec has been chosen as most other boards do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM specifier required the period cell. This patch adds it to all
Silabs based boards. Since all occurrences are PWM drive LEDs, a period
of 20 msec has been chosen as most other boards do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM specifier required the period cell. This patch adds it to all
Nuvoton based boards. Since all occurrences are PWM drive LEDs, a period
of 20 msec has been chosen as most other boards do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period was 255 nsec, a value that doesn't make much sense when
driving an LED. Since the period cell is rarely used nowadays, the
value was probably copy&pasted or a random value was added since it is
required. A period of 20 msec has been chosen as most other boards do
for PWM LEDs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Updated all PWM specs to include the period cell. Because all specs
refer to PWM driven LEDs, a period of 20 msec has been chosen, as most
other platforms do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Increase the size of the flash storage partition from 2KB (one page) to
4KB (two pages) in order to support NVS.
Fixes: #44977
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit enables rng for nucleo_l073rz platfrorm. This has been
tested with tests/drivers/entropy/api and is working as expected.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
The period was set to 60 usec, a value that doesn't make much sense in
the context of PWM driven LEDs. Since the period cell was rarely used,
the value was likely added because it is required, but was never used. A
period of 20 msec has been chosen as most other boards do.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
enable dma on rt1170 and rt1160 evk, since edma driver has been updated
to place TCD pools in correct location
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SOCs using the EDMA IP that supported caching must locate EDMA transfer
control descriptors (TCDs) in non cacheable memory. For M7 cores, this
can simply use the "nocache" section. For M4 cores, where the nocache
section does not exist, the chosen SRAM section must be a tightly
coupled memory block which cannot be cached. Add a note to all boards
with M4 SOCs that support caching explaining this issue, and enable EDMA
driver to locate TCDs in SRAM.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds audio dmic to the boards dts and a regulator
to enable the microphone VDD and L/R pin.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
Align the board dts with the recent changes in the "nordic,nrf-sw-pwm"
binding (remove the no longer existing `channel-count` property) and
add a node representing the edge connector for convenient referring
to SoC pins connected to it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... and "nordic,nrf-sw-pwm" binding:
- add `channel-gpios` property with GPIO assignments for PWM channels
to `sw_pwm` nodes
- use channel indexes instead of pin numbers in `pwms` properties that
define PWM LEDs
- add the period and flags cells to `pwms` properties in all PWM LED
definitions; use the commonly used period of 20 ms (giving 50 Hz)
as a default setting
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... and "nordic,nrf-pwm" binding:
- use channel indexes instead of pin numbers in `pwms` properties that
define PWM LEDs
- add the period and flags cells to `pwms` properties in all PWM LED
definitions; use the commonly used period of 20 ms (giving 50 Hz)
as a default setting
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit f4a0ddd8af.
Since the yellow LED and the SCK line of spi2 use the same pin
(P0.13), they cannot be used together. Consequently, the pin
should not be assigned to the same PWM instance as other pins
that drive LEDs, as the limitation of usage would apply to the
whole PWM instance (it acquires all the pins assigned to it on
initialization of the PWM driver, regardless of whether the PWM
signal is eventually generated on particular outputs or not).
Use a separate PWM instance (disabled by default) for driving
the yellow LED. Don't use the "nordic,invert" property for that
PWM, as the yellow LED is active high.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit f4a0ddd8af.
According to the schematic, the LED connected to the P1.09 pin is
active high. Therefore, the PWM1 instance that is configured to drive
the LED should not use the "nordic,invert" property.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
According to board documentation: "By default System
clock is driven by the MSI clock at 48MHz."
This is in line with rcc node dts configuration:
&rcc {
[...]
clocks = <&clk_msi>;
[...]
};
Though pll node is currently enabled, which is not in line with
current dts clocks description scheme and results to compilation
issue in clock_control driver.
Remove pll node configuration to fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move where the default value of `CONFIG_UART_CONSOLE` is set from
`Kconfig.defconfig` to `qemu_cortex_a9_defconfig`. This conforms to
the standard location and lets the default be overridden by
applications.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Nucleo F030R8 has some board revision.
Add revision configuration to support C-01 board version.
This commit add revision '1' and '2'.
Defaultly uses revision '2' that is for C-02 (or later).
This is uses existing configuration.
Set board name in west command option as 'nucleo_f030r8@1'
to use C-01 board.
C-01 has no supply clock to HSE, Must use HSI for SYSCLK.
nucleo_f030r8 clock configuration is
8MHz (HSE freq) / 1 (PLL prediv) * 6 (PLL mul) = 48MHz (SYSCLK)
In case of using HSI (added as nucleo_f030r8_ver_c01),
8MHz (HSI freq) / 2 (PLL prediv) * 12 (PLL mul) = 48MHz (SYSCLK)
PLL prediv is must take 2 if using HSI.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This commit adds missing yellow led and missing PWM leds.
This was verified with samples blinky, blinky_pwm,
fade_led and rgb_led.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
update pin control implementation to use offsets for pin registers
instead of pin/port combination, to permit additional flexibility for
lpc devices with non contiguous register layouts. Update LPC55s69 pin
control names to align with newly generated pin control header.
This change also requires an update to the NXP HAL to use the new pin
control headers with offsets.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix spelling errors in assorted .rst files. The errors were found
using a tool called 'codespell'.
Signed-off-by: Aleksandar Markovic <aleksandar.markovic.sa@gmail.com>
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
This commit adds support for the Arduino Nano 33 BLE Sense board.
The DTS is separated into a common dtsi and one DTS for each version
of the board. The sensors with existing drivers: hts221, lps22hb and
apds9960 are added to the DTS of the Sense version.
A startup delay is added to the vdd_env node. This is done to give some
time for the sensors VDD/VCC to go high before the sensor drivers are
initialized.
The functionality was verified using the driver sample of each sensor.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This extends the DTS for Arduino Nano 33 BLE with the nexus node for
pin mapping according to the binding for arduino-nano-header-r3.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@huawei.com>
Enables the flash controller node for the stm32u585 disco kit
with an arbitrary definition of the board partitions
to fill the 1MB bank1 of the flash memory,
for the secure and non-secure targets.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Correct the following errors in rddrone pinmux:
- Pin selection for UART4 RTS line was incorrect, should use PTE27
- Pin selection for red PWM LED was incorrect, should use PTD1
- FlexCAN0/1 RX should not have pullup resistors (per prior pinmux.c
settings)
- FTM0_CH1_PTA4 does not require a pullup resistor
- LPUART0_RX_PTD8 requires a pullup resistor for UART RX to work
Fixes#44314
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added required config for the display operation and default display name
to "LTDC" for LVGL subsystem when the peripheral LTDC is used.
Signed-off-by: Konstantinos Papadopoulos <kostas.papadopulos@gmail.com>
Onboard display is actually an ILI9341. It is connected to SPI5 which
is shared with L3GD20. Max clock is set as described in BSP driver files
(stm32f429i_discovery.c@638). ILI9341 configuration updated to enable
RGB interface use.
Signed-off-by: Konstantinos Papadopoulos <kostas.papadopulos@gmail.com>
This configure and connect host /dev/pts/N to arm qemu uart-1. It can
use a real device like /dev/ttyS0. Just switch config between serial
and pty chardev options.
In addition, this update QEMU_EXTRA_FLAGS to use only variables instead
hard coded values.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Add the period cell to GD32 PWM compatible and update all boards
accordingly. A period of 20 ms (50 Hz) has been set for all PWM LEDs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The board had PWM LEDs defined in the blinky_pwm sample, mainly because
it conflicts with SPI1 pinmux. A better approach is to still define the
PWM LEDs in the board but keep the PWM controller disabled by default.
Then, samples just need to enable the PWM controller (and disable SPI if
used simultaneously).
Also updated period to 20ms (reasonable value for a PWM-driven LED).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
