Add test case for all drivers that are supporting the die temperature
feature, and fix right away all the yet undiscovered issues.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
When we are sending a network pkt, do not tweak the original
packet but the cloned one. The original behavior is ok too, but
logically we should adjust the cloned packet only that is being
received by the stack. This also means that we avoid one extra
copy to tmp variable when sending the packet.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
This fixes the return error code for Preset Write operation that shall
be returned when preset is not writable (or disabled via Kconfig like in
this case).
As per HAS_v1.0; 3.2.2.3 Write Preset Name operation
"If the Writable bit in the Properties field of the preset record which
is identified by the Index parameter is set to 0b0, then the server
shall return an ATT_ERROR_RSP PDU to the ATT_WRITE_REQ PDU with
the Error Code parameter set to Write Name Not Allowed."
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
Rename xtensa_asm2.c to have a more meaningful name to actually
reflect the content of the file. This file is mostly about
handling interrupts and exceptions (via the predefined vectors
in Xtensa core).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fold z_arch_get_next_switch_handle() into return_to(). This is
not exactly an arch interface, and is simple enough to be
moved into return_to().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This follows the idea to remove any z_ prefix. Since MMU has
a large number of these, separate out these changes into one
commit to ease review effort.
Since these are no longer have z_, these need proper doxygen
doc. So add them too.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
z_xtensa_dump_stack() and z_xtensa_exccause() are both arch
internal functions that should not be exposed in public API.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
... from xtensa_asm2.c. Other architectures have
z_irq_spurious() and *_irq_is_enabled() test in irq_manage.c.
So follow the trend here.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
... from xtensa_asm2.c.
Everything has been stuffed inside xtensa_asm2.c where
they are all mangled together. So extract thread related
stuff into its own file.
Note that arch_float_*() may not be thread related but
most other architectures put them into thread.c. So we
also do it here.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_spin_relax() does not really fit into the scheme of
xtensa_asm2.c as it is mainly about handling interrupts
and exceptions. So move it into smp.c, similar to other
architectures which arch_spin_relax() defined.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
xtensa-asm2.h only contains the function declaration of
xtensa_init_stack() which is only used in one file. So
make the actual implementation a static function in that
file. Also there is really no need to expose stack init
function as arch public API. So remove xtensa-asm2.h.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
* Wording on CONFIG_SIMULATOR_XTENSA
* Remove "default n" as default is no anyway.
* Remove some tabs as we almost never indent inside a if block
in Zephyr.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no in-tree user. Also, it is misleading as we use
SCOMPARE1 for spinlock too, not just IPC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should be defined at the SoC
or the board level since Xtensa cores are high configurable.
The default is just for ISS (Instruction Set Simulator). So
remove it from the arch level.
The xt-sim board is the only one in tree that is targeting
the ISS, so add it there.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is supposed to stress the host buffer and metadata handling.
It is not really testing any particular thing, ie. the pass criteria is
just that each peripheral can send and receive a fixed number of GATT
notifications without any device crashing or locking up.
Original version by Ahmed Moheib (from cloud2ground).
Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
We follow the path of the header to define the guard, aarch32 was
removed some time ago and the guards still had AARCH32 in them, just
remove it and keep the guard consistent and short.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The `az3166_iotdevkit` board doesn't have its RTC node enabled,
and is failing the following test:
`tests/benchmarks/footprints/benchmark.kernel.footprints.pm`
Enabled RTC node for that platform.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The `96b_aerocore2` board doesn't have its RTC node enabled,
and is failing the following test:
`tests/benchmarks/footprints/benchmark.kernel.footprints.pm`
Enabled RTC node and lsi clock source for that platform.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix misplaced in,out in @param. If any parameters are output,
mark the others as input for clarity.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
z_free_page_count is only used in one file, so there is
no need to expose it, even to other part of kernel.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
How cache test could be ran without CONFIG_CACHE_MANAGEMENT?
Adding qemu_x86/x86_64 as cache related API in x86 has proven to be
very brittle against changes recently: no test was at least verifying
it builds properly, not to mention running it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without this, cache manipulation cannot work in x86.
clflush was introduced with SSE2 extension, but may be implemented
without this extension and it seems that qemu made this choice a
adding sse2 CPU capability does not include clflush. It enabled by
default in 64 bits, so let's take care of this capability only for
the 32bits version of the board.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Instruction cache related functions (see include/zephyr/arch/cache.h)
are not implemented in x86, thus let's not set CONFIG_CPU_HAS_ICACHE
which may end up in build failure if one sets CONFIG_ICACHE.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It did not build in x86_64 due to the fact that cr0 is a 64bits
register in such architecture, instead of being a 32bits one originaly
so the place holder has to follow that size. Such place holder must be
initialized to 0 to make sure no upper 32 bits ends up set which would
conclude in a general protection error.
Operand size specifier (l, q ...) is useless as well in this context.
Clearing up the masks by using proper macros.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
() Moves the architecture specific timing measurement APIs
under the timing measurement APIs group.
() Add SoC and board specific API groups.
() Document each SoC and board specific API so the doc shows up
for them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds two APIs which allow for configuring the cellular
network configuration of a cellular network device. like
a cellular modem. The first allows for configuring which
access technology to use, and optionally, which bands to
use. The second allows for getting all supported access
technologies are supported, and which bands for each tech
are supported.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Enforce that the initial attestation partition has the required
initial attestation key provisioned.
If the initial attestation key (IAK) is not present during boot of
TF-M the system will panic during initialization.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Introduce Kconfig option in zephyr build system that reflects the TF-M
cmake config variable with the same default value for dummy provisioning
and have it satisfy the IAK present requirement.
This configuration is not suitable for production, and by having this
in zephyr configuration we can have this as part of the hardened
configuration check.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Adds a charge_enable handler to facilitate enabling and disabling
a charge cycle. This deprecates enabling and disable the charge
cycle via the CHARGER_PROP_STATUS property.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
Changed the tx/rx pins in pinctrl *.dtsi files to match the
evaluation board circuit diagram for UART1.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
