Enable runtime mmio configuration in mcux_lpspi driver. The fsl_lpspi
driver relies on physical address to determine instance number.
So mmap flag 'K_MEM_DIRECT_MAP' is required.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Add return code to lpspi spi_mcux_transfer_next_packet and print the
kStatus_* return code since it information is lost when translated to
errno.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Changed how to get clock frequency for PL022
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This reverts commit bffa0c6bddbc91d39f4b01baa34e3d0595760d50.
This FIFO implementation causes a regression by which the SPI
peripheral generates several spurious SCK cyles after the last
data has been sent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Update documentation for SPI_NRFX_RAM_BUFFER_SIZE Kconfig symbol
to reflect new usage of it. Now the symbol specifies size of RX buffer.
The change introducing support for RX buffer placed by a linker in
memory region defined in SPIM devicetree node is in a parent commit
of that one.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
This patch adds support for RX buffer placed by a linker in
memory region defined in SPIM devicetree node. The buffer is placed
in memory region defined as devicetree node. The memory region node's
reference is then stored in `memory-regions` property of SPIM node.
Added build time assertion to check if `CONFIG_SPI_NRFX_RAM_BUFFER_SIZE`
Kconfig symbol has value greater than 0 when given SPIM node has
`memory-region` property.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The MCUX LPC driver now recognizes the complete_callback
flag. We need to set this flag so we receive a callback
after every block.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix error writing to the CR register on the first call to SPI configure on
NXP MKE1xF. On the first call, the module clock is not enabled and writing
to the CR register will fail.
Fixes: #66036
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Simplify and clarify spi_stm32_shift_m by splitting it in
3 smaller functions with clear names.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In H7, TXP indicates when its FIFO has room for, at least, one
packet. Thus, rename ll_func_tx_is_empty as ll_func_tx_is_not_full,
to be consistent in all platforms.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Avoind calling startMasterTransfer multiple times in a
transaction by moving it to the transceive() function.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
While enabling workaround for PAN 58 the PPI driver is used.
This requires the nrfx PPI driver to be enabled thus CONFIG_NRFX_PPI
Kconfig symbol needs to be set.
Jira: NRFX-1616
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This check has to be done independent of whether RAM is used for buffers
or not and depends on device maximum length property.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Instead of assuming only RAM is accessible by EasyDMA, use the generic
DMA accessible function.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Some targets may not have `NRF_SPIM_HAS_32_MHZ_FREQ` or
`NRF_SPIM_HAS_16_MHZ_FREQ` symbols but have `NRF_SPIM_HAS_PRESCALER`
symbol defined. The symbol informs that target supports 32 MHz and
16 MHz frequencies for SPIM instances.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The CLOCK HAL header is only needed for nRF5340 SoC. It's used when
user wants to configure SPIM instance to 32 Mbps. The HAL checks
if is running at 128 MHz as only then 32 Mbps is supported.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
In the case where a transaction is spilt due to the rx buff len
being longer than the tx or the transaction buffer exceeding the
size of the requested buffer with non gpio CS, the chip select
would be de-asserted/asserted in the middle of the transaction.
Fixes: #57577
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
For some STM32 MCUs the busy flag of SPI is unreliable. This is a known
issue of the device and described in the device errata.
As a fix implement a configurable timeout which ensures that a call
to spi_transceive will eventually return.
Fixes#64927
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Set Spi StateIndex equal to index of DT Spi node.
Because number of State array is set base on
number of DT Spi node used. If StateIndex is set
equal to Spi instance, StateIndex can be over array.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Fixes an unhandled interrupt runtime crash if CONFIG_SPI_XMC4XXX_DMA=y and
CONFIG_SPI_XMC4XXX_INTERRUPT=n.
The unhandled interrupt error is triggered because irq_enable() was called
without calling IRQ_CONNECT() when CONFIG_SPI_XMC4XXX_INTERRUPT=n.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In the interrupt driven spi, spi_context_update_tx() is called once
from the calling thread and then once in spi_xmc4xxx_isr() after each
new byte is received. This actually means that there is one extra call to
spi_context_update_tx(). This is fine if spi_context_update_tx() complete
it's call in the calling thread before the interrupt fires, however, this
cannot be guaranteed especially if the calling thread is pre-emptive and
has a low priority.
Fix this by calling spi_context_update_tx() in the calling thread before
transmitting the first byte.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new SPI shim driver for Intel SoCs. Builds upon the SEDI bare
metal SPI driver in the hal-intel module.
Co-Authored-By: Kong Li <li.kong@intel.com>
Signed-off-by: Ye Weize <weize.ye@intel.com>
Updated the Async API allowing the code path
for DMA while Async is enabled. Added common
DMA function that sets up both tx and rx dma
channels.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The instruction length can only be 0~5.
Use am_hal_iom_blocking_transfer and specify clearly the TX/RX direction.
Hold CS to continue to RX expected response after instruction transmission.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The commit fixes the SPI mode improper configuration.
Otherwise the MODE_3 and MODE_0 cases would never be entered as expected.
Signed-off-by: Aaron Ye <aye@ambiq.com>
SPI API allows `spi_buf_set` structures with no buffers linked to them
(with `.buffers = NULL`). Correct the spi_nrfx_spis driver so that it
is able to deal with such structures.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT, so
don't try to select the symbol if not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently, the driver imply understand that all instances
will use dma when CONFIG_SPI_MCUX_LPSPI_DMA is set. There
might be an instance doesn't need DMA, so instead of enforce
spi_transceive API to use DMA, add more flexible to enable
DMA only when required
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Modify STM32H7 SPI driver so that it updates the rx/tx
pointers correctly (depending on the frame size) when DMA
is enabled. Also, make the dummy rx/tx buffer cache-coherent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
