Information about IOAPIC can be located not in the first
DMAR Hardware Unit Definition subtable. Iterate them all.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add function walking though all DMAR subtables, at the moment only
first subtable is taking into account, which causes bugs for some
boards.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Fixes uninitialized variable return by returning zero
at the end of function.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
The implementation waited for a NET_EVENT_L4_CONNECTED event to be
emitted. However we can start the receiving thread in case the interface
is up.
This allows for IPv6 Link Local addresses to be used with mcumgr.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This code fixes following issue:
The TX data chunk (with NORX set) is send to chip (via SPI) and at the
same time a frame is received (by the LAN8651 chip), there will be no IRQ
(the CS is still asserted), just the footer will indicate this with the
rca > 0.
Afterwards, new frames are received by LAN865x, but as the previous footer
already is larger than zero there is no IRQ generated.
To be more specific (from [1], chapter 7.7):
----->8-------
RCA – Receive Chunks Available
Asserted:
The MAC-PHY detects CSn deasserted and the previous data footer had no
receive data chunks available (RCA = 0). The IRQn pin will be asserted
when receive data chunks become available for reading while CSn is
deasserted.
Deasserted:
On reception of the first data header following CSn being asserted
------8<------
Doc:
[1] - "OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface"
OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The description is a bit misleading as the packet is not even read in
the mentioned case by the OA TC6 Zephyr driver.
When the timeout occurs the data (packet) received by LAN865x may be:
- Read latter if still in the RX buffer of LAN865x
or
- Is (probably) dropped by LAN8651 itself as the RX buffer gets overrun
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The parity of the received footer from data transfer (also including the
NORX) shall be checked before members of struct tc6 are updated.
This prevents from updating the driver's crucial metadata (i.e. struct
oa_tc6) with malformed values and informs the upper layers of the driver
that error has been detected.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
With the current approach, the driver prevents from TX transmission
when waiting on timeout (standard 100ms) for available memory to be
able to allocate memory for RX packet.
It is safe to just protect the part of reading chunks. In that way
pending TX transmission can be performed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP boards with CMSID-DAP are not detected by twister
--generate-hardware-map, because serial device name 'mbed' is compared
with upper case 'MBED' in a list of supported manufacturers.
Fix it by making the comparison case-insensitive.
Tested using mimxrt1020_evk.
Fixes#63765
Signed-off-by: Michal Smola <michal.smola@nxp.com>
If the DT node for mdio of nxp enet has a mdc freq specified,
use this when configuring the module.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a property to the mdio controller binding to describe the MDC
frequency generated by the controller.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Implement the CAP Commander discovery function.
Adds support for it in the shell.
This includes initial babblesim and unit testing as well.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This PR corrects the RAM size specification of
the Infineon CY8CPROTO-062-4343W PSoC6 eval board.
Fixes#60876
Signed-off-by: Manuel Loew <manuel.loew.infineon@gmail.com>
Reworked and combined the multi-level interrupt bit masks tests
to work on any configuration of bits in every level.
Updated the bits configuration in the testcase to use
non-symetric numbers so that shifting a level with the wrong
number of bits will certainly cause the test to fail.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Rename the bitmask variables from `*_LVL_INTERRUPTS` to
`INTERRUPT_LVL_BITMASK[]` array to be consistent with
`INTERRUPT_BITS`, making it easier to loop over the bitmasks.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The calculation of `THIRD_LVL_INTERRUPTS` bitmask in the
`update_masks()` function is wrong, the number of bits to shift
should be the sum of the first two levels.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Update to the last relase of open-amp library
The libmetal is updated to a more recent commit to integrate
2 zephyr commits on top of the v2023.10 release.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Update west manifest to point to hal_stm32 PR containing changes
which allow to build a zephyr bluetooth application on STM32WBA.
Prior building such application, user should run 'west blobs fetch stm32'
to install binary blobs providing the BLE controller support.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
To be compatible with BLE operation and BLE Controler configuration,
update board clock configuration to work using a fixed core clock at
16MHz.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
We might have to do this differently:
Configure rng default clock in .dtsi
Set board specific config in .dts
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SRAM6 is used by RF and should be defined as RAM_NOCACHE
to allow unaligned access reads.
"IO" might be a better match but is not available on this arch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to enable BLE support on STM32WBA, following APIs are implemented:
- HostStack_: BLE Controller scheduling
- ll_sys_: Link layer API required for scheduling
- UTIL_TIMER_: BLE Controller timer utility
- LINKLAYER_PLAT_: BLE controller utilities
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The condition for channel-map are CONFIG_BT_CENTRAL ||
CONFIG_BT_BROADCASTER, change the corresponding handler ifdef so that
it's included in the build if CONFIG_BT_BROADCASTER is enabled but
CONFIG_BT_CENTRAL is not.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In init function, start timer with period CYC_PER_TICK if tickless is
not enabled, This change is for fixing the issue that disabling
CONFIG_TICKLESS_KERNEL the OS tick is not work issue, this
causes the OS not starting scheduling correctly.
Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
Imported the original Cooper (Apollo4x BLE controller) device files
from AmbiqSuite SDK 4.4.0 and adapts them to support the new
implemented HCI driver for Apollo4 Blue Plus.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The BT HCI uses internal IOM4 (SPI4) for communication bus.
Set the default configuration for BT based on the controller supported
capability and HCI driver dependency.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commits create the dts binding for Ambiq BT HCI instance.
And create the SPI based common HCI driver for Ambiq Apollox
Blue SoC and the extended soc driver for HCI.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Fix a possible race condition in the keyboard matrix library where a key
would get pressed between the last read and reenabling the (edge
sensitive) interrupt and the even would be lost.
The window for this to happen is very narrow and had to artificially add
a sleep to reproduce it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change the interrupt setup from both edge to edge to active. Edge to
active is all was needed anyway and it makes this compatible with gpio
controller that only support single edge interrupt.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit introduces `kconfig_to_ot_option` to simply fye the way of
adding openthread related kconfigs.
Signed-off-by: Przemyslaw Bida <przemyslaw.bida@nordicsemi.no>
The DC233C core has support for both i-cache and d-cache.
So mark it as such so we can test caching of Xtensa in QEMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With MMU enabled on Xtensa, user_buffer is not marked as
executable. Invalidating the i-cache by region will cause
an instruction fetch prohibited exception. So skip all
i-cache tests, instead of just the range ones to avoid
confusions of only running the test partially.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() arch_icache_line_size_get() needs to be inlined or else
compiler would complain that it is not being used.
() arch_icache_flush_all() returns -ENOTSUP not as there is
no xthal_icache_all_writeback() in HAL.
() Fix typo vid -> void in arch_icache_disable().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
