Commit a10fee2d5e (drivers: clock_control: ccm_rev2: add support for
reclocking FlexSPI) introduced the ability to set the FlexSPI
clock frequency at runtime on RT11xx series SOCs. However, this
implementation resulted in the clock frequency being rounded up, not
down. This can result in flash clock frequency violations on some
flash parts, causing the system to crash when running in XIP mode.
Fixes#69088
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When exiting PM_STATE_SOFT_OFF, the primary core state is always
used to restore bootctl register and the clock and power gating
settings.
This can lead to problems if non-primary core is powered up and down
many times before primary core 0 is powered down the first time.
The saved state in core_desc[0].bctl will be null, and as a result-
power gating and clock gating is not disabled correctly for
non-primary cores.
Link: https://github.com/thesofproject/sof/issues/8642
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Executing from RAM sections other than rom/code should cause a fault.
This is tested as part of the kernel mem_protect tests.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add initial support for the VPR RISC-V core found in the new nRF54 SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
nrf-regtool is a Python utility from Nordic Semiconductor, which is used
for generating binary files with register values for given peripherals.
It sources the descriptions of peripheral registers from CMSIS-SVD files
(typically ones bundled with nRF MDK).
For some peripherals, such as UICR, nrf-regtool supports parsing values
from devicetree as well, based on the bindings already found in Zephyr.
Currently, this tool is not submitted as a script to Zephyr, but it can
be installed from PyPI.
Having nrf-regtool installed is recommended when working with nRF54H20.
Booting the Application or Radiocore CPU requires flashing not only its
firmware, but also its respective UICR instance. On this SoC, the UICR
is used to assign ownership of global hardware resources, including
memory and peripherals, to individual cores. The Zephyr build system can
call nrf-regtool to generate the UICR based on devicetree, to reflect
the boot-time hardware configuration required for a given application.
The generated `uicr.hex` is then merged with `zephyr.hex`, so that they
can be flashed together using west.
The build system integration takes the form of a CMake package, which
includes a version check and reusable components; over time, some of
these components can be reused by sysbuild. This package is located in
the `hal_nordic` module, because it depends on the `SOC_SVD_FILE` CMake
variable, which is defined there as well.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add nrfx and Kconfig related infrastructure plus SoC initialization
code to allow building for nRF54H20 targets (Application and Radio
cores).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... to cover missing __ICACHE_PRESENT and __DCACHE_PRESENT symbols that
should be defined in MDK files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Consistently use `zephyr_library*` cmake functions for all nRF Series
and set the Cortex-M linker script in a common place for all of them.
Remove no longer needed include directories.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In nRF54L15 FICR can be accessed also from non-secure code,
so it does not have NRF_FICR_S defined.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
NRF_RTC_TIMER will not be a default timer in the next
version of Nordic timer. It should be soc selection specific.
Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
The RA_PINCFG macro is used to generate a value that can be written
directly to the pin function select register. In addition to the pin
function this value also contains port and pin number information,
located in bit fields that are unused by the register. The bit field
used to store the port information consists of 3-bits. However, a typo in
the mask definition limited the field to two bits meaning only ports 0-3
could be configured. This patch resolves the issue, allowing ports 0-7 to
be configured. If the port is greater than 7 another field (port4) is used
to store an additional bit (allowing an additional 8 ports to be
supported). However, use of this field has not yet been implemented.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
SOCFPGA_SYSMGR_REG_BASE base address now read from Device tree
This commit changes the way the SOCFPGA_SYSMGR_REG_BASE base address is
determined. Previously, the address was hard-coded in the system_manager
source file. This commit changes the code to read the address from the
Device tree. This makes the code more flexible and allows the base
address to be different for different boards.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
In pm_state_set we can't just call k_cpu_idle() because
this will clear out PS.INTLEVEL. Use k_cpu_atomic_idle instead
since Zephyr's expect interruptions to be locked after pm_state_set.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We are arbitrarily setting a value to PS after power gates and
losing valid information like OWB, CALLINC and INTLEVEL.
We need to properly save/restore them to avoid possible wrong behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
ROM configures the ISP boot pins as gpio to determine what boot mode to
be in. But some ROM revisions have a bug where they do not restore the
reset state of these pins before booting application. This can cause
power leakage on these pins and is not an intended configuration from
Zephyr user/board point of view, so restore the reset state as part of
early SOC init (disable the pins). Configuration of pins should be
left up to app/board devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The OpenTitan PLIC has support for up to 255 interrupt vectors, so
set it to that. Previously was set to number of IRQs used.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
There is default 15K-ohm pull-down for USB controller.
To disable the default pull-down to avoid signal contention in GPIO mode.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Only when CONFIG_MP_MAX_NUM_CPUS > 1, then .bss is put in
uncached region. Otherwise, .bss is in cached region.
So the assertion that g_key_read_holder must be in uncached
region must take into account how many CPUs are enabled on
build.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Commit 3b99fb1b4a ("xtensa: do not imply atomic ops kconfig") removed
ATOMIC_OPERATIONS_ARCH at xtensa arch level. This triggers a bug in
intel_adsp cavs builds with XCC compiler as
CONFIG_ATOMIC_OPERATIONS_BUILTIN is not defined but neither is
CONFIG_ATOMIC_OPERATIONS_ARCH anymore, resulting in failed builds.
Fix the XCC build by defining CONFIG_ATOMIC_OPERATIONS_ARCH at
soc level.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This allows to link code and data blocks, e.g. the vector table, into
tightly coupled memory using `zephyr_linker_sources`.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
With the introduction of the SAI and EDMA drivers, there's
no longer a need to map the MMIOs using the mmu_regions.c
method since this is taken care of by the drivers via
device_map(). As such, remove entries for EDMA and SAI from
mmu_regions.c.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
