S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.
Note that the cache controller is not available for S32K11x devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.
Fixes#66147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce support for NXP S32K1 family of 32-bit MCUs, and
particularly for S32K146 devices. S32K1 share a fair amount of
similarities with Kinetis family, so most of the peripheral drivers
can be reused.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
