The tsim executable is named tsim-leon3, tsim-leon4, tsim-gr716, etc.
This is needed to find the emulator program for twister to do the run
step.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Since frdm_k64f is used as example in mcumgr sample with serial transport,
make it ready for compilation.
Fixes#63520
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Minor updates both to make it more consistent with the
nrf53bsim documentation, and include more links
and a small section about the C library choice.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Update the documentation describing the bsim boards overall
to match the current reality.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add documentation for the newly introduced nrf5340bsim boards.
And rename the nrf52bsim documentation file as it is not the only
one anymore.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Minor updates as now we have also native_sim, so we
should not only refer to native_posix.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This reverts commit 8084ea55b7.
The rootcause is fixed in the ARC QEMU which is in SDK 0.16.3.
As we've updated SDK in upstream CI we can revert this
workaround.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Zephyr's code base uses MP_MAX_NUM_CPUS to
know how many cores exists in the target. It is
also expected that both symbols MP_MAX_NUM_CPUS
and MP_NUM_CPUS have the same value, so lets
just use MP_MAX_NUM_CPUS and simplify it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Update flashing information for npcx7m6fb_evb and npcx9m6f_evb since
current OpenOCD in zephyr-sdk has supported them.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
While recent browsers seem to transparently try to use https when
hitting http://www.cypress.com/... URLs, they are effectively not
working anymore, so use https://www.cypress.com/... URLs instead. And
it's a good practice anyway to promote secure links vs. plain http :)
curl http://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 -v -m 5
* Trying [2a02:26f0:2b00:1a::212:b1ac]:80...
* Connected to www.cypress.com (2a02:26f0:2b00:1a::212:b1ac) port 80
(#0)
> GET /products/32-bit-arm-cortex-m4-psoc-6 HTTP/1.1 Host:
> www.cypress.com User-Agent: curl/8.1.2 Accept: */*
>
* Operation timed out after 5004 milliseconds with 0 bytes received
* Closing connection 0 curl: (28) Operation timed out after 5004
milliseconds with 0 bytes received
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Support code coverage on all RISC-V qemu targets. Additional
boards may choose to enable coveage support as well.
Tested by following the procedure documented at
https://docs.zephyrproject.org/latest/develop/test/coverage.html
with the qemu_riscv64 target.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
This is the more useful document to point newer Zephyr users to.
The support documentation template is already mentioned in the guide
(under "Contributing your board"), but leave the existing link to it for
quick reference, just changing a few words.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This prepares support pwm capture APIs by extended current pwm
shim driver but use a differrence hal component:
- Introduce a Kconfig options that will be set when PWM pulse
generation API is used, it is also used to select the hal
component. Guarding current code inside this Kconfig option
- Increase #pwm-cells to 3, flags is supported for PWM capture
- Do not require duty-cycle and polarity be set in dt, PWM
capture doesn't need it.
- Rename emum value for pwm-mode to keep only key information
- Add preprocessor in case no channel is configured for generate
PWM output, to avoid warning when build
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
So it gets the command line arguments by default.
This eases running the BT test which run on the
nrf52_bsim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Automatically start the Network domain CPU during HW boot.
In the real HW this CPU is held on reset until something else
(Typically the application MCU) releases it.
But doing so facilitates running tests in this MCU as there is
no requirement for an image for the application core.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
When we have more than 1 MCU, add the MCU number to the traces
so we can identify from which MCU they come from.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add options to force MCUs to boot/not boot, overriding
of how they would behave otherwise, as well as an
option to print info about the MCUs present in the
platform.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
As a development helper, add a kconfig option to
automatically start the MCU this Zephyr image is built
for during HW boot, even if in other circumstances
this MCU would not start automatically (for ex. because
another core is meant to release its reset).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
As we will now we having more nrf5*_bsim boards defined in this
same folder, the old folder names became missleading.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
To allow knowing for which MCU are the options,
prepend them with the MCU number.
The primary/preferred MCU will also keep an alias to the
old options (without the cpu<n>_ prefix)
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Each MCU hooks need to be named according to its MCU number.
Rename the hooks appropriately.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
To be more accurate, as this option represents a microcontroller
number, not a CPU number.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Assign DMA channels/sources for all LPUARTs exist on the
board so that async APIs can be used for all instances
when enabled.
Because LPUART 1 & 9, LPUART 2 & 10 share the same DMA
sources for TX and RX, be aware when using async APIs
for those instances.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Some Ethernet PHYs used the devicetree node name `phy`, while others
used `ethernet-phy`. Be consistent and use `ethernet-phy` throughout.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
* In Zephyr:
* The HW models now include N fake timers, and N
bst timers.
The embedded code needs to target the one for its
CPU specifically.
* Update the HW models module to
f4595802d32d103718bf50b3d390b7a450895843
Including the following:
* f459580 TEMP & ECB: Fix INTEN sideeffect prototypes
* 50c2abe nrfx_common: Fix build error with clang
* 5f0ae29 FICR: Add nrf53 variants
* 82ee9bd DPPI: On initialization, set all registers to their reset value
* 1472c34 NVMC & UICR: Readied for nrf53
* f425c08 NVMC & UICR: Refactor
* 3a4cfc2 RADIO: Parametrize ED_RSSIOFFS
* a20e9fc nrfx_get_irq_number() Add missing CCM peripheral for nrf5340net
* c199715 DPPI: Bugfix
* 93806ac Zephyr cmake: Align with nrf53 board rename
* 51f26a3 VREQCTRL: Add register stub and definitions for nrf53
* 802e0cf RADIO: Switch to level interrupts, readied for nrf53
* 49bcea2 Templates: Added shortcut check & event signaling version for s
* a880cd6 Template: Move static out of signal handler definition
* 709f82b TEMP: Switched to level interrupts, readied for nrf53
* 6ef0069 AES_CCM: Switched to level interrupts, readied for nrf53
* eaa89da RNG: Use common templates
* 75a6cb4 AAR: Switched to level interrupts, readied for nrf53
* fbf58f3 AES_ECB: Switched to level interrupts, readied for nrf53
* d084647 RNG: Bugfix in STOP subscription
* 8007318 Templates: Added template code for the most common models logic
* bab6a54 int ctrl: Added new API
* daaaaa0 config: Fix nrf53 Net core EGU instance HAL mapping
* 54570a0 nrf5340 RTC int mapping fix
* 043af26 nrfx_common: Provide nrfx_get_irq_number() for 5340 cores
* ecd7b9b SWI: Add SWI pseudo peripheral
* a70c73b CLOCK: Add missing TASK sideeffecting prototypes, and fix typo
* 56c7581 nrf5340: Split HAL files in net and app sets
* 3892d3e Add API to get the MCUs/domains names
* 8f485bc RADIO: Prevent clang build warning
* 5aac1c2 hal: Build weak version of the HAL for the 53 series also
* f18422d standalone nrfx_config: Provide needed definitions for nrf53
* 4015d5a nrfx_glue_bsim: Provide 2 trivial definitions for standalone bu
* 4af80d5 cmsis stubs: Provide trivial macro to replace ISB
* b6c2769 cmsis replacements: Fix for other Zephyr bsim targets
* 8316930 zephyr CMakefile: Set HAL version based on Kconfig
* 4404106 RNG: Rename functions to match new naming convention
* a3dbb38 RTC: Rename functions to match new naming convention
* 886dc73 CLOCK: Rename functions to match new naming convention
* bcb2b99 EGU: Rename functions to match new naming convention
* 50af67e TIMER: Rename functions to match new naming convention
* 8120224 CLOCK/POWER/RESET: Add DPPI connections, generalize to N instan
* 450337c RTC: Add DPPI connection, nrf53 support and new functionality
* 2918ce6 DPPI common subscription: Minor API change
* ec1c2a7 TIMER: Add DPPI connection, nrf53 support and functionality
* e6f9860 EGU: Add DPPI connection, nrf53 support and generalize
* c8a4368 bst_ticker: Generalize to N instances
* 093deee fake timer: Generalize to N instances
* 302da8d DPPI: Typo fix
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a new kconfig option to be able to pass extra images to the
native simulator build.
So one can, for ex., use one application build to produce one core image,
and at the same time have it produce the final link with the native
simulator runner and the other MCU images.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The Zephyr build leaves all kconfig options as absolute symbols
in the image. This need to be localized, otherwise they will
appear as duplicates with other Zephyr images.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The platform is known for having unstable system timer with networking
enabled (see https://github.com/zephyrproject-rtos/zephyr/issues/48608)
causing occasional failures of time-sensitive networking testsuties
(TLS, now DHCPv6). Instead of excluding the platform on per-test basis,
just exclude the platform from networking testing globally.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Update the descriptions for the various CAN devicetree timing properties
specified in Time Quanta (TQ) to make it clear that these, if present, are
only used for the initial timing parameters.
Deprecate the (Re-)Synchronization Jump Width (SJW) devicetree properties
for both arbitration and data phase timing as these are now only used in
combination with the other TQ-based CAN timing properties, which are all
deprecated.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adjust model names and compats for Intel alder-lake boards. Names are now
consistent with names used in other Intel boards.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add `mdio_read_c45()`/`mdio_write_c45()` APIs for Clause 45 access
and remove the `protocol` MDIO binding property so that MDIO bus
controller can support more than one protocol.
A new MDIO header is introduced with generic opcodes, MMD and
registers addresses, to be used by MDIO and PHY drivers.
Existing MDIO drivers that support both Clause 22 and Clause 45
access are migrated to the new APIs.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This renames the board from qemu_xtensa_dc233c to
qemu_xtensa_mmu to better signal that it is for testing with
MMU on QEMU Xtensa. Also turn on testing by default to make
sure future changes will not break Xtensa MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
