Fix for Issue#35658.
Update the custom vector table to add the OS Event timer
interrupt which is used on RT685 as the kernel system timer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The stm32_lptim driver is hardcoded to use lptim1.
Make the Kconfig option depend on the presence of the node label in the
devicetree, so that there's one less list of supported SoC to keep track
of.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
In npcx series, we use ITIM64 as system kernel timer. Its source clock
frequency must equal to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This CL
added check during initialization to prevent ambiguous condition.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Make the APIC_TIMER_IRQ_PRIORITY Kconfig depend on APIC_TIMER ||
APIC_TSC_DEADLINE_TIMER to hide it in menuconfig when not applicable.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
As per description of the sys_clock_elapsed() function, "the kernel
will call this with appropriate locking, the driver needs only provide
an instantaneous answer". Remove then the unnecessary locking from the
function, as it only adds an undesirable delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Replace suffix ull to ULL to increase code readability and prevent
unexpected behaviours, because the lowercase character l shall not be
used in a literal suffix
Found as a coding guideline violation (MISRA R7.3) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
With this patch the sys_clock_set_timeout function counts the cycles
elapsed while computing the systick timer's new load (tickless mode).
This cycles are then added to the total cycle count instead of being
lost.
This patch mitigates uptime drifting in tickless mode (especially when
high frequency timers are registered).
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
-ENOSYS should be returned if the operation is not implemented. This
issue was causing some PM tests to fail, as -ENOSYS was expected.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt. Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic. The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default. Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").
Really this is just ideal for Zephyr. So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead. All modern hardware has
what it needs. The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Remove the config BOOT_TIME_MEASUREMENT and corresponding #ifdef'd code
throughout (kernel/init.c, idle.c, core/common.S , reset.S, ... ) which
hold the extern hooks for z_timestamp_main and z_timestamp_idle in the
removed boot_time test suite.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
During polling ITEN bit to make sure ITIM timer is enabled, we might
have the chance that npcx_itim_evt_enable() return fake error when
timeout expired but ITEN bit is set already if CONFIG_ZERO_LATENCY_IRQS
is enabled. (Since SVCall's interrupt priority is not the highest, the
other interrupts with IRQ_ZERO_LATENCY flag could preempt CPU resource
at this moment.)
In order to prevent return fake error code, this CL adjusts the check
conditions for ITEN bit and timeout.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
There was an inconsistency in the API as z_nrf_rtc_timer_chan_alloc
returned int but other function were using uint32_t for channel
argument. Updated api to use int32_t everywhere.
Update nrf_802154 driver which was using this api to use int32_t.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).
The support is based on the Cortex-M33 support that already exists in
Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This feature predated the tickless kernel and has been in legacy mode
for a while. We now have no drivers or systems that do not support
tickless, so remove this option and cleanup the code to only use
tickless.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The clock/timer APIs are not application facing APIs, however, similar
to arch_ and a few other APIs they are available to implement drivers
and add support for new hardware and are documented and available to be
used outside of the clock/kernel subsystems.
Remove the leading z_ and provide them as clock_* APIs for someone
writing a new timer driver to use.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
If next_timeout() returns INT_MAX and pass it to
z_clock_set_timeout(), and machine goes to freeze or slow down.
Bad scenario as follows:
- If an argument int32_t ticks is set large value 0xffffffff,
ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);
replaces it into MAX_TICKS.
- uint32_t cyc will be set near by 0xffffffff
(this is 0xfffd7280 in 100 ticks per second).
- Add adjustment to cyc, adjustment max value is MAX_CYC.
(cyc = 0xffff14fd)
- Over 0x80000000 value of uint32_t is considered as negative
value of int32_t.
if ((int32_t)(cyc + last_count - now) < MIN_DELAY)
This condition is always true.
- Because cyc += CYC_PER_TICK will get overflow, driver sets mtimecmp
near value of current mtime.
(cyc = 0x00007fc0)
- Next timer interrupt will happen soon after return from interrupt
handler.
- By repeating these events, machine cannot go to next instruction,
and it's going to freeze or slow down.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Use timeout mechanism instead of unbounded loop during enabling ITIM32
module which source clock is LFCLK (32KHz).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Qemu when running more than one processor has a known synchronization
bug where counter values read from the HPET (notionally a single
global device) can be seen going "backwards" when read from different
CPUs.
There was a pre-existing workaround in the ISR that knew about this,
but the problem can crop up anywhere the counter value is used. In
particular I caught it aliasing with the "max_ticks" computation in
z_clock_set_timeout(), where it would cause a rollover and the
resulting negative comparator value would result in no end of
hilarity.
Wrap all access to the counter register with a counter() inline that
(when the workaround is enabled) forces the result to be monotonic by
clamping it to a minimum of one more than the previously read value.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This include make possible to use the arm_arch_timer on
platform such as Cortex-A9 or Cortex-R7 which has support for
ARM Global Timer.
The global timer is a 64 bit incrementing counter, memory-mapped
in the private memory region.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The count register is 64 bits, but we're a 32 bit CPU that can only
read four bytes at a time, so a bit of care is needed to prevent
racing against a wraparound of the low word. Wrap the low read
between two reads of the high word and make sure it didn't change.
Fixes#31599
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
idle is only considered in other timer implementations if ticks ==
K_TICKS_FOREVER but in arm_arch_timer. Just fix it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
TICKLESS_CAPABLE is now selectable only and without prompt, so remove it
from _defconfig files and select it directly by the timer.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_timer_idle_enter is declared only when CONFIG_TICKLESS_IDLE is
selected. This function is not implemented anywhere, but the only
driver including this header is not TICKLESS_CAPABLE. So, no undefined
reference will happen.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
