Refactors all of the serial drivers to use a shared driver class
initialization priority configuration, CONFIG_SERIAL_INIT_PRIORITY, to
allow configuring serial drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The one
exception is uart_lpc11u6x.c which previously used
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS.
This change was motivated by an issue on the frdm_k64f board where the
serial driver was incorrectly initialized before the clock control
driver.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
ARM Server Base System Architecture defines Generic UART interface,
which is subset of PL011 UART.
Minimal SBSA UART implementation does not define UART hardware
configuration registers. Basically, only FIFOs and interrupt management
operation are defined.
Add SBSA mode to PL011 UART driver, so it can be used at SBSA-compatible
platforms, like Xen guest.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert older DT_INST_ macro use in arm_cmsdk/arm drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a fixed clock to the qemu-virt-a53.dtsi to match how the musca dts
files work so we get the clock DT info in the same way in the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In the DT_INST conversion we introduced a typo bug of accessing port0
instead of port1 in the IRQ config function.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The PrimeCell UART (PL011) IP can use one single combined/shared
interrupt line instead than different IRQ lines for TX/RX/Err/... This
is the most common configuration supported in the Linux world but not
currently supported in Zephyr. QEMU emulates a PL011 UART with a single
interrupt line as well.
To support this configuration we have to hookup the PL011 driver with a
shared IRQ driver and add two new configuration options when the shared
IRQ line is used.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The driver fails to compile when CONFIG_UART_INTERRUPT_DRIVEN=n. This is
due to a nested ifdef on CONFIG_UART_INTERRUPT_DRIVEN that is excluding
pieces of code unrelated to the uart interrupts management.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The PL011 driver is not specific to the cortex_m arch and the driver
does not really use anything from the cmsis header file. Remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The uart_pl011 driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
move uart.h to drivers/uart.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch changes the ICR masking to use a fixed mask instead of
a buggy read/write of the current ICR to itself. The ICR is write
only and reading this for information is unpredictable and should
be avoided.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds a serial driver for the ARM PL011 IP block.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>