This commit adds a flash driver implementation that writes to RAM and
exports statistics through stats.h. It can be used to simulate flash
memory for testing purposes.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Add driver and device tree binding for the Low Power Inter-Integrated
Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The MCP2515 is a CAN controller that can be connected via SPI to an
host MCU. This driver adds support for the MCP2515 as a new driver in
the CAN subsystem.
As it is a SPI peripheral it uses a thread for its interrupt
handling and the received message filtering is done inside this
interrupt thread, as the MCP2515 filter capabilities are not sufficient
for the Zephyr CAN interface.
The driver was validated with an external CAN logger and the adjusted
CAN sample application.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Fixes: #14513
This commit move the functionality of extracting zephyr modules into
generated CMake and Kconfig include files from CMake into python.
This allows other tools, especially CI to re-use the zephyr module
functionality.
Signed-off-by: Torsten Rasmussen <torsten.rasmussen@nordicsemi.no>
As the author of the latest rework of the counter driver API,
@nordic-krch is a more appropriate person than me to be the codeowner
of this driver.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
When the console UART is a PCI device, and PCI debug logging is enabled,
the system crashes because the UART is initialized before logging, but
the UART initialization invokes the PCI subsystem which invokes logging.
Reordering the initialization sequence will not fix this chicken/egg.
Luckily, the LOG_DBG() calls in the PCI subsystem appear to be bitrot
leftovers from early development, so they are simply removed.
Also mark myself as the owner of the PCI subsystem.
Fixes: #14763
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add framework for device Idle Power Management(IPM)
for suspending devices based on device idle. This will
help in saving power even while system(CPU) is active.
The framework uses device_set_power_state() API set the
device power state accordingly based on the usage count.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
If CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT is enabled,
the app shared memory partition may cause waste of memory
due to the need for padding.
For example, tests/subsys/jwt and board mps2_an385:
z_test_mem_partition: addr 0x20000000, size 52
z_libc_partition : addr 0x20000040, size 4
k_mbedtls_partition : addr 0x20008000, size 32736
ending at 0x2000ffff, taking up 65536 bytes
With power-of-two size and alignment requirement,
k_mbedtls_partition takes up 32KB memory and needs to be
aligned on 32KB boundary. If the above partitions are
ordered as shown, there needs to be a lot of padding
after z_libc_partition before k_mbedtls_partition can
start. In order to minimize padding, these partitions
need to be sort by size in descending order.
After the changes here, the partitions are:
k_mbedtls_partition : addr 0x20000000, size 32736
z_test_mem_partition: addr 0x20008000, size 52
z_libc_partition : addr 0x20008040, size 4
ending at 0x2000805f, taking up 32864 bytes
With the above example, sorting results in a saving
of 32672 bytes of saving.
Fixes#14121
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Pull in libmetal SHA 59a10acbb0bb684c1a75488f11878cb984170c81 to get
some build fixes related to newlib.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Following new shield introduction in #14057, it has been highlighted
there was no codeowner for boards/shields/.
Assign erwango as codeowner.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Running checkpatch in pre-commit hook could be a constraint
for day to day work. Though, running it before pushing to
zephyr repo is highly recommended.
Add a series push script callable from pre-push hook.
Document how to use it in contribute section.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The mbedtls library has some globals which results in faults
when user mode tries to access them.
Instantiate a memory partition for mbedtls's globals.
The linker will place all globals found by building this
library into this partition.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The settings tests was not properly covered in terms of maintainership,
add maintainers for the corresponding subystems.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
- PR #13722 moved 3 gen_*.py to /arch/x86/ without updating CODEOWNERS
- PR #13745 forgot a trailing slash in /dts/bindings/can
- PR #13675 forgot a trailing slash in /samples/boards/intel_s1000_crb
No idea why github doesn't keep reporting these every time and
impossible to tell as CI hides most of its logs.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Storage was not properly covered in terms of maintainership, add
maintainers for the corresponding subystems.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
I already did a bunch of POSIX API related work, and integration of
BSD Sockets API, etc. with full POSIX subsystem will require further
more work.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
