The block data length field should be in bytes. Setting this to a value
that is not a multiple of the data size results in a user setting error.
Running the ADC DMA test prior to this commit:
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/adc/adc_dma
E: Transfer Error.
I: tc: 0, ht: 0, dte: 0, ule: 0, use: 1
E: DMA sampling complete, but DMA reported error -5
Existing tests using DMA on the nucleo_u575zi_q were not effected
because they only use a data size of one and continue to function
as expected:
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/spi/spi_loopback \
-DOVERLAY_CONFIG="overlay-stm32-spi-dma.conf"
SUITE PASS - 100.00% [spi_loopback]: pass = 1, fail = 0, ...
west build -p -b nucleo_u575zi_q zephyr/tests/drivers/dma/loop_transfer
SUITE PASS - 100.00% [dma_m2m_loop]: pass = 3, fail = 0, ...
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
The tables for the dest and src data width constants were incorrectly
swapped. This commit uses the correct constants and renames the tables.
This change is only cosmetic for the stm32u5 since these constants are
the same but the existing names were probably inherited from another
driver where the p_*/m_* prefix was more appropriate.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
Enable DMA error interrupts so that transfer errors are logged and
reported to the callback.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
Add a second instance of DMA to the stm32 dma driver from the DTS
That can be found in the stm32H5 serie, where 2 GPDMA with 8 channels
are available. Rebuilding with Macro.
Use the dma_channels property of the dedive tree to count the nb
of dma channels: 16 or 8 (like in stm32h5).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On a repeated dma_start, the stm3u5 dma driver should return
immediately if it is already started.
On a repeated dma_stop, the stm3u5 dma driver should return
immediately if it is already stopped.
This like the dma driver does for other stm32 series.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the resume API function for the dma driver of the stm32U5 serie.
That completes the suspend API function.
Controlling the SUSPF bit of the GPDMA CR register is enough
to suspend/resume the channel.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There is no need to reset the channel else DMA config is lost and
channel should be enabled again in case of resume.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Gives the stm32u5 dma driver a suspend function to
enhance the dma API.
This is a particular feature of the stm32U5 GPDMA
to suspend a channel.
A delay is required ;1ms is compatible with both stm32u5 platforms.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For the stm32U5 serie, the busy flag is handled as other serie.
When the DMA is overriden by other HAL drivers, the busy flag
is not considered.
Refer to https://github.com/zephyrproject-rtos/zephyr/pull/47645
There is no Mux for this GPDMA and fixed 16 channels.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix the scope of some variables in various STM32 drivers including:
- SDMMC
- DMA
- OSPI/QSPI Flash
- Interrupt controller
The variables are set static instead of global and const if appropriate.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
It includes the definition for the DMA peripheral of this type,
present on stm32U5 devices.
A particular DMA_STM32U5 config is selected for that purpose.
The driver is derived from the existing dma_stm32.c
The GPDMA is counting channels (0-15) ; stream offset is 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
