ssize is a POSIX.1-2001 extension, which may or may
not be provided by the C library, or may be defined
to a different size in the host and embedded C library.
Two internal functions were returning ssize.
As these functions were just trampolines
into the same host API, which are already provided
by the native simulator let's just use those.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This change adds support for enabling ethernet MAC hardware checksum
offloading for STM32H7 based devices.
In Section 58.5.9 of the STM32H7 reference manual it mentions that
the STM32H7 ethernet MAC supports a Checksum Offload Module (COE).
I have tested the changes on my end where I enabled
CONFIG_ETH_STM32_HW_CHECKSUM and ensured that an application that
runs Zephyr on the STM32H7 can interoperate with a device with a
completely different implementation. Also, I deliberately made
the software not populate the IPv4 and UDP header checksum fields
in their respective headers and the COE was able to populate the
IPv4 and UDP header checksums.
Given that CONFIG_ETH_STM32_HW_CHECKSUM is not enabled by default
application developers have the option to either enable it or
disable it.
Signed-off-by: Chamira Perera <chamira.perera@audinate.com>
This code fixes following issue:
The TX data chunk (with NORX set) is send to chip (via SPI) and at the
same time a frame is received (by the LAN8651 chip), there will be no IRQ
(the CS is still asserted), just the footer will indicate this with the
rca > 0.
Afterwards, new frames are received by LAN865x, but as the previous footer
already is larger than zero there is no IRQ generated.
To be more specific (from [1], chapter 7.7):
----->8-------
RCA – Receive Chunks Available
Asserted:
The MAC-PHY detects CSn deasserted and the previous data footer had no
receive data chunks available (RCA = 0). The IRQn pin will be asserted
when receive data chunks become available for reading while CSn is
deasserted.
Deasserted:
On reception of the first data header following CSn being asserted
------8<------
Doc:
[1] - "OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface"
OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The description is a bit misleading as the packet is not even read in
the mentioned case by the OA TC6 Zephyr driver.
When the timeout occurs the data (packet) received by LAN865x may be:
- Read latter if still in the RX buffer of LAN865x
or
- Is (probably) dropped by LAN8651 itself as the RX buffer gets overrun
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The parity of the received footer from data transfer (also including the
NORX) shall be checked before members of struct tc6 are updated.
This prevents from updating the driver's crucial metadata (i.e. struct
oa_tc6) with malformed values and informs the upper layers of the driver
that error has been detected.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
With the current approach, the driver prevents from TX transmission
when waiting on timeout (standard 100ms) for available memory to be
able to allocate memory for RX packet.
It is safe to just protect the part of reading chunks. In that way
pending TX transmission can be performed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Improve code readability of this driver by simplifying and reworking
some of the source code, formatting and comments.
This commit is not meant to cause any functional difference.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Configure to grant SI permissions to allow to set MAC,
update hash filter table and promiscuous multicast.
Fixes#66198
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Need to do the ENET module-level clock initialization from zephyr
instead of MCUX HAL, because now there are multiple zephyr drivers with
different init priorities that rely on the module being clocked. MDIO
must be initialized before the ENET MAC, and the MAC driver currently
calls ENET_Init from the HAL to initialize the clock, but MDIO needs the
module clock enabled first on some platforms. So replace the MAC init
with ENET_Up from the HAL, which doesn't include clock init, then do
clock init from a higher priority sys init based on the parent
compatible.
Also, add support for enet clock ungating with clock_control_on on ccm
driver do this with current platforms supported.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- PHY can be set up as rmii but still use 25 MHz MDC, add DT property
value for this case
- Fix KSZ8081 driver spamming phy status in debug level logging,
and fix some other state/logging logic
- Fix PHY driver not rescheduling monitor work if first configuration
fails, change code path to use goto for errors
- Handle case where some phys are not using the gpio pins in phy driver
Make GPIO properties of ksz8081 phy optional since these hardware pins
may be unused on some boards
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the handler of SI Rx event within
the shim driver itself.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
When there'is no phy at the address both registers will return
0xFFFF, giving a phy address of UINT32_MAX, not 0x00FFFFFF.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The 62833 added a regression at SAM ethernet drivers which always fail
to initialize due to a wrong switch case implementation and without
review from maintainer. This add more information and fix the issue.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Simplify the driver header implementation, so that there are not
structs and unions different per each situtaion, and make just one
function for the enet module drivers to call on each other. Also,
capitalize existing enums.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The NET_L2_ETHERNET_MGMT configuration option is required to allow
setting MAC address or PLCA parameters with the LAN865x driver.
To avoid mistakes with per-board configuration files - it has been moved
to Kconfig and automatically selected when the driver support is enabled.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Handle the situation when OA TC6 compliant device signals to the host
that its configuration is lost - i.e. the SYNC bit in the footer is
cleared.
In this (unlikely happen) situation the device is reset and reconfigured.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
As part of IRQ service routine, there is at least one data transmission
performed between OA TC6 compliant device and HOST uC.
As this transmission can happen when there is no valid data to be read
(and its only purpose is to deassert the interrupt) the DV bit in footer
may be cleared. As this situation is expected with this approach - the
LOG level can be safely lowered from error to debug.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
According to the OPEN Alliance 10Base-T1x standard (point 7.7), it is
mandatory to read at least single data chunk (no matter if received data
is valid or not) to deassert the interrupt in the LAN865x (then the tc6
structure fields are also updated from the footer).
Current approach with reading OA_BUFSTS register was providing the
required information (RCA and TXC), but could cause transmission "stalls"
as this operation (i.e. control, not data transmission) is not causing
deassertion of the interrupt IRQ_N line from OA TC6 compliant device.
With this patch - the transmission is always performed at least once, so
interrupt is always deasserted.
As the functionality of oa_tc6_update_buf_info() - i.e reading value of
RCA and TXC - has been replaced with extracting data from footer, this
function can be safely removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In case of boards where REF_CLK signal is not connected
to the GPIO0 by default add the possibility to use
the optional GPIO16/GPIO17 as a REF CLK source.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
NSEC_PER_SEC is an unsigned literal which will promote variable increment
to unsigned for the comparison operation, thus returning -EINVAL for
negative increment values.
For positive increment, -NSEC_PER_SEC becomes a large unsigned value
which will also return -EINVAL.
Fix by casting NSEC_PER_SEC to an int.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
This commit provides support for changing PLCA parameters stored in
lan865x_config_plca structure.
After values are updated, the LAN865x needs to be reset and then
configured with new values.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The LAN865x device after HW reset supports only the non-protected control
transmission mode. When it is reset alone - without resetting already
configured HOST system - one must assure that in HOST's OA TC6 driver
the protection SPI transmission support is disabled.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The ctx->reset member of struct lan865x_data shall be cleared each time
one wants to reset the LAN8651 device.
Before this change this value was only initialized in the lan865x_init().
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change allows modification of the PLCA configuration in the lan865x
driver.
Values in this structure can be set via device tree as well as modified
by the user program.
Without this change the latter use case would not be possible as the
struct lan865x_config structure is defined as read only and its data
is only provided by device tree.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add driver for NXP ENET which is a rework of the old
eth_mcux.c driver which had become unmaintainable due to
fundamental problems with the lack of PHY abstraction.
eth_mcux.c and the corresponding compatible nxp,kinetis-ethernet
will be deprecated and this new driver will be supported instead.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add Driver for KSZ8081 Ethernet PHY. The Generic MII Driver
is not sufficient to use for this PHY chip which has special
vendor implemented behaviors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a property to the ethernet controller binding
indicating what type of connection the MAC has with
the PHY device.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
The code to handle OA TC6 compliant device's status is generic and can
be moved to device agnostic driver (oa_tc6.c).
Moreover, the original code has been augmented with LOG_WRN() messages.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change fixes semaphores' definition. To be more specific - the
limit was wrongly set to UINT_MAX. With those changes - the 'tx_rx_sem'
now assures that only one execution path (i.e. receiving or sending
data) is executed at a time.
Moreover, the change in 'int_sem' now assures that this semaphore limit,
when reached, is saturated.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit ensures that whole receive function (called from interrupt
handler) is protected by the RX/TX semaphore.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The oa_tc6_update_buf_info() function returns error code when read
(protected or not) of OA_BUFSTS has been detected.
In that situation - one shall re-start the interrupt thread handling
(and hence correctly re-read value of this register) than use old
(stalled) RCA(RBA) data to read chunks (which may result in lockup).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Current code sends extra, last chunk, when packet's size is a multiple
of chunk size (i.e. 64 bytes).
This patch fixes this issue by checking this corner case - i.e. if
the modulo division equals to zero.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The RCA and RBA fields in OA_BUFSTS register are stored with 8 bits each.
On the other hand, when one receives those values in footer, the value
is saturated to 5 bits due to 32 bit size constrain of the footer itself.
To avoid any mismatches - the values read from OA_BUFSTS are saturated
as well.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Zephyr's network stack has issues with network IP header split across
fragments.
To alleviate this problem, the frame would be now aligned to first byte
of the chunk. This would ensure that the header is stored at one network
buffer fragment (as we explicitly set its size to 64B).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The OA TC6 driver requires some bits manipulations in control registers.
Up till now - it has been implemented as an explicit set of read and write
registers' operations.
One good example would be the oa_tc6_set_protected_ctrl() implementation,
which used such scheme.
This patch brings dedicated function for this operation; oa_tc6_reg_rmw().
The aforementioned oa_tc6_set_protected_ctrl() function now uses it
internally.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add the missing dependency of the node status value
and enable the driver by default when they are met.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
This driver assumed the ivshmem-v2 output sections would be mapped
contiguously, which is no longer true.
Modify eth_ivshmem to treat each output section independently
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Regression failure introduced problem where driver code was not properly
wrapping code that only existed when compiled for IPv4/v6 applications.
Fixes#65549
Signed-off-by: David Leach <david.leach@nxp.com>
This moves the k_* memory management functions from sys/ into
kernel/ includes, as there are kernel public APIs. The z_*
functions are further separated into the kernel internal
header directory.
Also made a quick change to doxygen to group sys_mem_* into
the OS Memory Management group so they will appear in doc.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC header already includes the necessary device headers for
all SoC variants supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
