Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
In order to enable BLE support on STM32WBA, following APIs are implemented:
- HostStack_: BLE Controller scheduling
- ll_sys_: Link layer API required for scheduling
- UTIL_TIMER_: BLE Controller timer utility
- LINKLAYER_PLAT_: BLE controller utilities
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The DC233C core has support for both i-cache and d-cache.
So mark it as such so we can test caching of Xtensa in QEMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Definition of ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT,
which is used in the intel_adsp_force_dmi_l0_state function,
is missing.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
Currently on zephyr, RAIL library is used only by Bluetooth applications,
with this update, it will be able to be used for sample applications
for custom radio phys.
All files were copied from Silicon Labs GSDK v4.2.4.
Signed-off-by: Zoltan Havas <zoltan.havas@silabs.com>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Separating two new functions force and allow l1
to have the current state with separated functions
in the ipc file so that SOF can call these
functions via IPC DMI_FORCE_L1_EXIT. Change related
to the addition of a new parameter to force
DMI L1 exit on IPC request.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This follows the idea to remove any z_ prefix. Since MMU has
a large number of these, separate out these changes into one
commit to ease review effort.
Since these are no longer have z_, these need proper doxygen
doc. So add them too.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.
Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Use the already available in the tree mechanism of adding assembly
instructions right after WFI/WFE to implement the workaround for
nRF5340 anomaly 168 (replace the 4 NOP solution used on the network
core as it turned out to be insufficient) and provide two related
Kconfig options so that users are able to adjust the workaround to
their actual needs (disable it entirely or use it in the extended
version).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Enable the TF-M NS storage partition for nordic boards.
This partition is otherwise not used, and configured as secure.
Fixes: #59376
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.
Note that the cache controller is not available for S32K11x devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update the Kconfig for the npcx eSPI driver so it's automatically
enabled if the devicetree node is enabled.
Signed-off-by: Keith Short <keithshort@google.com>
Microchip's PolarFire SoC (MPFS) has 186 available interrupts.
Fix the Kconfig symbols.
While we're at at: remove commented out code
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
GCLK Gen 2 was dedicated to USB, but never setup... this patch
configures it for 48 MHz, derrived from DFLL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.
Fixes#66147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Some SoC have missing feature selections in their Kconfig.
Some others are missing includes of CMSIS-Core headers.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This changes remove extraneous includes causing issues with cycles in
includes subsequently having code requiring definitions from CMSIS
while it’s configuration hasn’t completed yet.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Kconfig parameters, header’s default & silicon vendor’s SDK configuration
for CMSIS Core, must be consistent. Depending on the inclusion order of
the headers, this is currently not always the case.
This change introduces consistency checks & enusers defaults match their
Kconfig settings.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
