Some SPI based displays expect the ability to lock the SPI bus after a
transaction completes, or to hold CS low. In order to accommodate this
within the MIPI DBI layer, add the mipi_dbi_release API, which allows
SPI displays to hold then release the SPI bus used by the MIPI
abstraction layer.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce NXP LCDIC driver using MIPI DBI class. This peripheral
supports 8080 and SPI 3/4 wire mode, although only SPI 4 wire support is
currently implemented. The driver supports DMA and interrupt driven
transfers.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Taking a spinlock will result in interrupts being blocked in the MIPI
DBI driver, which is not desired behavior while issuing SPI transfers,
since the driver may use interrupts to drive the transfer
Fixes#68815
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add cleanups to pin presence checks within the mipi_dbi SPI driver.
The cleanups now verify that GPIO and RESET pin devices are ready,
if they are present for the device instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal
Beyond this, MIPI DBI operates in 3 modes:
Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus
Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus
Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
