Device sync APIs are actually wrappers for semaphores.
Let's replace them with semaphores.
Jira: ZEP-1411
Change-Id: I02c7cba21d21ff9288e452121e3b7ebb7d251bb4
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I28789a7f1f26e4a0d499f5a89a567ae8c61eae51
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
Drivers that implement power management should use the preferred
device_pm_ops method instead.
Change-Id: I337722b1e06afe8508b5c84c00c3542571232e07
Signed-off-by: Iván Briano <ivan.briano@intel.com>
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
A recent submission caused a build error for DW
CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE because the symbols
CONFIG_SPI_<0,1>_IRQ went missing from Kconfig.
I think these should probably NOT be configurable, because
on an SOC, interrupt lines are hard. So I'm changing
the names back to SPI_DW_PORT_<0,1>_IRQ, with there
definitions originatig in the soc.h file.
Also, on DesignWare ARC EM Starterkit, the SPI interface
has 6 slave selects, but IP itself can handle up to 16.
Why does this start from 1 and not 0? Argh!
DBG_COUNTER_RESULT() should expand to 0 when not used.
Also, don't check version from DesignWare IP because
it can be different for each target.
spi_dw_isr() requires a cast when converting arg to dev.
Change-Id: I83d55e0405583e7cafab80b09cbef44e0f96fcb8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Use the same Kconfig infrastructure and options for all SPI drivers.
Jira: ZEP-294
Change-Id: I7097bf3d2e1040fcec166761a9342bff707de4dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Most of the values are SoC specific and come from the SoC definition,
not need to define them in Kconfig.
Jira: ZEP-294
Change-Id: I962ce36b7e2361ea77ae4178bb7c86c19a241c4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not have priority per IP, use one config instead.
Change-Id: Ieb2923d4749a294e2a1c677d47d56a14cee3f36d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Note that the failure case can only be reached when compiling
for ARC side of Quark SE. Otherwise, the code is never compiled
which reduces code size for other platforms.
Change-Id: Ic76890cbaf22da5c3563e056cba9b39615d3da0c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SPI API states:
"max_sys_freq is the maximum frequency supported by the slave it
will deal with"
However, currently, for DW the max_sys_freq is a divider which confuses
the user.
This patch adds a small hack to allow users to use both dividers and
frequencies when configuring the bus. The only trade-off is one has to
use dividers for bus frequencies smaller than 65536Hz. However, since
most devices nowadays can run at clock frequencies more than 100kHz,
this is a good compromise.
Change-Id: I44386cc8ad501b08eeaf71bc7588661ff36e108b
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
This patch replaces all occurences of the macro DEV_NOT_CONFIG by
-EPERM at the driver level. This patch is part of the effort to
transition from DEV_* codes to errno.h codes.
Change-Id: I3054c8aa76319a58a2eec089b8a72bf301c85391
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_USED by -EBUSY
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I21eb3ffe9bdfde98593dcf63c50a8bdcd376e49e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_CONF by
-EINVAL at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: Idae0d5af8dd780416977c9261a5fb6188c3aab64
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_FAIL by -EIO
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I0594ab5dbe667e074c250129e7c13ce512ac940f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_OK by the actual
value 0 at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I69980ecb9755f2fb026de5668ae9c21a4ae62d1e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
There's no reason to require callers to cast their data to uint8_t *
when the data might e.g. originate in a packed struct or some other
data type. Instead, be nice to callers and let them use any pointer
they want. Additionally, declare the TX buffer as a const pointer so
unnecessary typecasts aren't needed for that either (if the data
originates in a const location).
Change-Id: I1482ca4e350b5a7fbda6871ed9f54f255af3aa9e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The buffers aren't guaranteed to be aligned so that they're always
aligned for uint16_t or uint32_t data. Use the available unaligned
access macros to read/write the data.
Change-Id: Ie87c108aa370af196b9c759b59ed7fb9d1ed6183
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Available only when CONFIG_SPI_DEBUG is set:
- Print out all exported functions with relevant infos
- Remove superfluous messages
- Make counter in push/pull not being instanciated when not debugging
Change-Id: Iaa96a897008d360a14bc83da54152c264f42c60d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It's a bug that did not happen, but is a valid one:
if there is an error, we should not care at all about current stage of
transmission, thus it will stop right away.
Change-Id: Iec2b519d8118233f570ded18d6c6eb4084371e5b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename them to DEVICE_NAME_GET and DEVICE_GET to fit in the 'device'
namespace.
Change-Id: I407a7f284ed4d1c071961b46615eea859c2e825f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename them to device_sync_ to fit in the device_ namespace.
Change-Id: I1088dda958584ed90b97137298050fee44c20ee4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Reading: As when setting up the transfer, Rx has to adapt to current
left Tx lenght.
Writing: If nothing will be transmitted anymore, downsizing the level to
0. This fixes a hanging issue while making the controller being busy for
nothing. Another hack found to fix the same issue was to test the SR
Busy flag bit in the ISR handler. As the threshold level makes more
sense, kepping this one.
Change-Id: I87ba393d507c9418295f188d866d9979f423536c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Controller should not be enabled while configuring or setting up a
transfer call. It's enabled once the transfer call is ready to proceed,
and disabled once the last interrupt has be raised.
Change-Id: Ib9125a3600971b57e642730682f2b3bfb91b1e02
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On Quark SE, SPI might require GPIO to be ready before hand, to emulate
CS, thus providing an option to tweak the intialization priority for SPI
DW driver.
Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It might be necessary to emulate CS through a GPIO pin depending on
these 2 conditions:
- the controller's CS pin is not wired, and thus a GPIO pin is the only
option
- The controller is unstable at a certain frequency and cannot set/unset
CS reliably. This is actually a possible issue on DesignWare's SPI
controller in Quark SE or Quarks D2000 where it has been found
unstable at 1Mhz and above.
Change-Id: Ib6a06577906c005ddd347070d476a367a9c3da8a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Refine how DFS is calulated now that it is strictely used to
manipulate buffer lengths.
- Fix threshold limit
- Tune RX threshold relevantly (reduce it if rx_len is lower than actual)
- Don't push more than available left space in FIFO
- Tune the private structure to lower memory space occupation
Change-Id: I65b1b48b996b2104cebcb24cc366fb4dcbf7d53b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On ARC, the SPI IP block might be accessible only via user extended
auxiliary registers, which requires different instructions to read from
and write to.
Change-Id: I3aa5f223938a9aed7795de4aedc64bd529d62942
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Registers offsets are hopefully all the same, but size differs.
On x86, thus 32bits support, CTRL0 or DR for instance are 32 bits r/w.
And DFS on 32 bits support is placed differently as well.
Change-Id: I5115d5c3c9bba71ece4a6f4a1d3d2fdc203c8da1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Only 8 bit frames were supported. Added support for bigger data frames
which can go up to 32 bits (on 32bits version of the controller, 16 bits
otherwise). Store the frame size in bytes during configure, and use it
during pull/push to read/write correct frame size.
Change-Id: Iae8c55442e0a205403aa3febd1811b36aaf4c5b6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
