When the loopback drops driver packets, the number of dropped
packets is counted and can be requested externally.
Signed-off-by: Sjors Hettinga <s.a.hettinga@gmail.com>
Incorrect GPIOTE channel was being freed because the pin number
being used is not the absolute pin but the pin within the port.
Signed-off-by: Wael Barakat <waelsbarakat@gmail.com>
Add inclusions of header files with devicetree related ADC definitions
to the nRF SoC dtsi files so that those definitions can be used also
for nRF SoC based boards.
Provide definitions of nRF ADC and SAADC analog inputs suitable
for use in devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add 'inversion-on' property to st7735r.
Issue INVON(21h) command on initializing if inversion-on was enabled.
As a result of this command, the display color is inverted.
Otherwise, INVOFF(20h) will be issued.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
There is no need in the `flag_quad_io_en` field.
When QE enabling failed, then the driver `init` fails as well.
There is no way to use qspi in quad mode if qe is not enabled.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds support for 1-4-4 and 1-1-4 read modes.
SFDP is used to query for available read instructions, then the
fastest one is used.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Renames 4PP define to PP_1_4_4
* Adds PP_1_1_4 define
That matches linux kernel defines a bit more.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
On STM32WB and dual-core STM32H7 MCUs, the RNG peripheral is shared
between the cores and its access is protected by a hardware semaphore.
Locking was not performed in the current entropy driver, leading to a
race condition when multiple cores concurrently used the RNG. This
commit implements the necessary logic for locking the HSEM during entropy
generation on multi-core STM32 MCUs. It also reconfigures the RNG in case
the configuration was changed by the other core, as this can happen e.g
on STM32WB MCUs.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Some sockets (UDP sockets at least) do not generate "<N>,CLOSED"
messages when the WiFi network drops. As a result the networking stack
thinks these sockets are still open after the network has dropped, and
after any subsequent reconnections.
This affects the DNS resolver library in particular, which leaves UDP
sockets open permanently by default.
Manually close these sockets when the network drops to ensure a clean
state the next time the network connects.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
`esp_close_work` can be queued from the `on_cmd_closed`, which clears
`ESP_SOCK_CONNECTED` and sets `ESP_SOCK_CLOSE_PENDING`, but does no
further work. The receive callback should still be run with no data when
the socket is closed through this mechanism.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Use the dedicated `DT_INST_STRING_TOKEN` macro instead of manually
retrieving `DT_DRV_INST`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Xilinx AXI UART Lite v2.0[1] has the following clause for both RX and TX
FIFO respectively:
When a read request is issued to an empty FIFO, a bus error (SLVERR) is
generated and the result is undefined.
When a write request is issued while the FIFO is full, a bus
error (SLVERR) is generated and the data is not written into the FIFO.
To protect this, we have:
xlnx_uartlite_read_status(dev) & STAT_REG_RX_FIFO_VALID_DATA, and
xlnx_uartlite_read_status(dev) & STAT_REG_TX_FIFO_FULL
but these are not enough for multi-threaded apps. Consider two threads
calling poll_out(), it is always possible for a thread to be swapped out
right after reading the status register, the other thread fill the TX FIFO,
and the original thread is swapped back to write more data to the FIFO
because previously read status doesn't indicate the FIFO is full.
To close this race condition, this commit uses a spinlock for each FIFO.
This ensures that only one thread accesses the FIFO even for SMP cases.
This closes#45302.
[1] https://docs.xilinx.com/v/u/en-US/pg142-axi-uartlite
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Add pin control support to gpio_imx driver, so that GPIO pin muxes will
be selected when the use configures a pin as GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add additional pin controller settings for iMX application core SOCs, as
well as a "fallback" pin control setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Simplifies the driver and Gives a generic function to prepare the Regular
commands for each instruction.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the stm32 octospi driver based on the exisitng quadspi
for stm32 devices and source code from the STM32Cube.
This drivers initialized the peripheral and the NOR memory
in SPI or OctoSPI mode with STR or DTR data Transfer rates.
The NOR-flash can provide the SDFP table directly (if supported)
or through the DeviceTree.
Limitation: no DMA transfer.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With the introduction of the OSPI NOR flash controller
more octal commands and parameters are defined.
It completes the existing SPI commands
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Whenever EC bootloader already configured a pin as output and
high, any further reconfiguration via pinctrl driver causes a
glitch in said pin with current sequence.
Defer pin direction configuration to be last operation over
gpio control register to avoid the glitch.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Log a message when the modem asynchronously closes a link. This is
useful information to the user as it can explain the root cause of later
failures.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx eSPI and host_subs driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx adc driver. Please notice users need to
configure the corresponding pinctrl nodes in 'pinctrl-0' property in the
adc0 DT node. For example, if ADC0 and ADC2 channels are selected for
the application, please add the follwoings in your board DT layout file.
&adc0 {
status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx tachometer driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in ps2 driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in pwm driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in i2c driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in uart driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update the MCUX ELCDIF driver to use CONFIG_MCUX_ELCDIF_POOL_BLOCK_NUM
for the number for frame buffers to allocate.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
