Added intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS UART, SPI and I2C for
transfer and receive operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Added support for 64bit address source and destination
usage for dw common.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
CFG register uses fields that are not defined in Synopsys databook of
Designware AHB DMA Controller.
Since current Zephyr code uses this driver only for the
intel_adsp_gpdma driver I assume that those fields are specific to
this DMA which is not the standard Designware one.
This patch allows to use either the standard Designware register or
the Intel one.
Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai>
Add a helper function to dump the GPDMA SHIM and channel registers for
debug along with a config option to enable it.
Co-developed-by: Tom Burdick <thomas.burdick@intel.com>
Singed-off-by: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
For Intel ACE1.x the GPDMA link list structure should be aligned
to 64 bytes to avoid the link list entry fetch crossing the 64 bytes
address alignment.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Multiple instances of the device would have inadvertently shared the
LLI pool potentially causing nasty bugs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Ports the SOF DesignWare DMA code to Zephyr.
Effectively replaces much of what was the designware driver as this
driver enables scatter gather which the older driver did not.
* Enables cyclic transfer description lists when the cyclic config
param is given.
* Enables linear link position usage with cAVS GPDMA.
* Passes suspend/resume, scatter/gather tests.
* Provides status updates of the transfer through dma_get_status()
* Enables reloading a cyclic transfer with dma_reload()
* Enables dma handshakes using the dma_slot config param.
* cAVS specifics remain in the dma_cavs_gpdma driver.
Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Co-authored-by: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
It turns out XCC didn't like this change as it doesn't have a
__COUNTER__ builtin. Bummer.
This reverts commit e8389f2f53.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Makes the IRQ_CONNECT macro statically declarable for Xtensa (nothing
prevented it except its structuring). Allows for IRQ_CONNECT usage
on a xtensa only platform to be declared statically avoiding the
fluff of setting up and enabling irqs for cavs gpdma.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Move most of the designware driver into a common compile unit with a
a header that exposes the common functionality.
This allows for derivative hardware, such as that in intel's adsp (cavs)
to use the common functionality while extending.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
