The init struct for DMA peripheral is allocated in stack
and must be initialized (e.g. with LL_DMA_StructInit here)
to avoid loading undefined values in the DMA peripheral
registers.
Signed-off-by: Abel Radenac <a.radenac@lacroix-sofrel.com>
Refactors all of the DMA drivers to use a shared driver class
initialization priority configuration, CONFIG_DMA_INIT_PRIORITY, to
allow configuring DMA drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Not all STM32 parts have at least 5 DMA interrupt vectors for DMA2. In
particular, some STM32F1 XL-density devices only have 4 DMA2 interrupt
vectors, with Channels 4 and 5 sharing the same vector. Added
#if DT_INST_IRQ_HAS_IDX(1, 4) to prevent compiler errors on these SoCs.
Signed-off-by: Josh Hansen <jhansen3141@gmail.com>
fixes peripheral drivers such as async uart that rely on dma being
ready failing because dma is not initialized yet.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
The code was wrongly calling DMA_Abort on a channel
that not initialized. This fixes Issue#38078
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
In the dma.h there is a dma_ctx structure using a magic code
to be identify. This structure must be prepared as a new
element of the dma_stm32_data.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the configuration of the stm32h723 where the
dma1 & dma2 of type V1 with a MUX. Even if DMA is of type V1,
the 'feature' does not exist with DMAMUX
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The flag source_periph seems to be incorrectly set in dma_stm32.
In case the transfer direction is from periph to mem, then the
stream->source_periph is 1 (true) else it is false.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the dma V2bis which is particular DMA V2 instance for
stm32F1 and STM32L1 soc series. This DMA does not use the dma slot
Otherwise it is similar to version V2.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In stm32l5xx soc, the LL_DMA_InitTypeDef has 2 more fields
(DoubleBufferMode and TargetMemInDoubleBufferMode) that must be
initialised with 0 else the configuration is wrong and gives
wrong values to the LL_DMA_Init function. Due to this the test
tests/drivers/dma/loop_transfer too would fail.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
The STM32F0 MCUs (except STM32F030XC) don't have a DMA channel selection
register (DMA_CSELR). This patch fixes the build of the dma_stm32 driver
for them.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
The request id is given by the DMA request MUX id which start at offset
1 and are vaid until req_nb + gen_nb.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit continues simplifying the generation of
isActiveFlag/clearFlag funtion pointer array for the request generators
and does the same for the table_ll_channel.
Additionally move struct dmamux_stm32_channel to c file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit uses dt property dma-channels instead of ll defines to
make sure every soc has correct number of function pointers defined.
While commit 5f6218a tried to fix this for g0 series, this caused
regression for other series(e.g. stm32g431). Using UTIL_LISTIFY and
dt properties this should finally be fixed and reduce boilerplate code.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
1. Update the SDK API's called in the configure implementation.
The DMA_PrepareTransfer and DMA_SubmitTransfer SDK functions
are not recommneded for use. Replaced the call to these SDK
functions with other SDK API's.
2. Fix the implementation the configure function when multiple
blocks are used.
3. Update the dma_reload implementation. The old reload function
would simply abort the transfer. The new implementation reloads
the DMA buffers for transfer.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix stm32_dma_is_irq_active not checking the IRQ status(IsEnabled) for
active interrupts.
While the transfer-complete, half-transfer comp. and transfer-error
is_XX_irq_active() functions check for IRQ status (IsEnabled),
ORing the result with dma_stm32_is_gi_active() overrides the
status check as gi is always 1 in case any of these flags is active.
Related to commit 96c92ed93f.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use LL_DMAMUX_CHANNEL_x defines instead of DMAMUX_CSR_SOF7x to check
if corresponding LL_DMAMUX_IsActiveFlag_SOx and LL_DMAMUX_ClearFlag_SOx
inline functions exist and should be added to func_ll_is_active_so[]
and func_ll_clear_so[].
The HAL of some socs uses the same flag to decide which registers exist
on a specific soc. And the same defines are used for table_ll_channel[]
initializations.
This is necessary because DMAMUX_CSR_SOF5 and DMAMUX_CSR_SOF6 were
wrongly added in the HALs soc header file for some stm32g0 socs,
therefore without this change some stm32g0 socs couldn't compile.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update the existing driver to support STM32G0 series.
It enables the DMA_STM32_SHARED_IRQS flag for g0 series, such that
all interrupts are handled in a shared isr to avoid irq conflicts.
The shared isr is extended to be able to handle irqs from more than one
dma instance.
Furthermore the config_irq function of instance 1, which connects to the
irqs, was reworked to avoid irq conflicts when 2 dma instances on
stm32f0, or stm32g0 are enabled:
While dma1 has one exclusive irq for channel 1, and one irq for dma1
channels 2 and 3, all other channels share the same irq.
Therefore it is currently not possible to enable dma2 without enabling
dma1 at the same time, without getting an build errror due to an irq
conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Not all STM32 Series can enable a dedicated clock for dmamux.
In stm32g0 series for example the clock is enabled automatically
as long as either DMA1 or DMA2 is enabled.
This commit changes dmamux driver to cope with socs that don't have
defined a clocks property. Therefore it moves the config(and data)
struct into the c file to be able to use DT_INST_NODE_HAS_PROP macro.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the missing parts for adding support
to stm32h7 dma driver.
The fix is to make dmamux driver work with
dma v1 driver.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
1. remove redundant protection on channel status
2. update link interface to support major and minor link
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Enable half transfer interrupt of the dma controller
in case the channel was enabled in circular mode.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Increase BD buffers from 7 to 9 to handle 1024 block
counts having mega/normal src,dst bd combinations in one request.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Sync packet is always CARD to HOST and if it's combined with HOST
to CARD transfers in one single RM header packet, it's not allowed
due to RM implementation constraints. RM implementation allows same
type of data transfer direction in all the BD's populated under one
header BD.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Zero initialize the ch_handle in dma_pl330_configure().
The memset in dma_pl330_config_channel()is incorrect,
as the ch_handle is already populated with valid values and
the dma_pl330_config_channel() is overwriting with zeros.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
All dma drivers are devicetree based now so we can remove the last
bits of Kconfig associated with the old driver style.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Conver the NIOS-II mSGDMA driver to be devicetree based. Add node for
dma controller into nios2f.dtsi.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When running the tests of the async api of uart
on nucleo-l4r5zi we get MPU fault.
The reason is ordering initialization. The uart and dma
drivers are initialized PRE_KERNEL_1 while dmamux is
initialized POST_KERNEL.
Thus, the function device_get_binding fails since the
dmamux device is not ready to be used.
Fixes: #32715.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Move dmamux_stm32_channels struct from device data to device
configuration and initialize the dmamux channel - dma channel
assignment during build time,
as this association is hardwired in all known series.
The information is taken from dma_offset and dma_requests device tree
properties. The current implementation is valid for series with either
a single or two dma peripherals and a single dmamux peripheral.
Both dmas can independently enabled.
As the driver uses multi-instance DT_INST_DEFINE, also macros for a
second dmamux are are added that should allow easier extension to a
second dmamux instance.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Drivers are using DEVICE_AND_API_INIT which is deprecated so convert
the iproc_pax dma drivers over to using DEVICE_DT_INST_DEFINE and
DEVICE_DT_INST_GET.
Fixes#32153
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When checking for IRQ flags, we should also check
for IRQ status (IsEnabled ?).
If this is not done we can end up in Half Transfer
interrupt processing while it is not enabled.
Additionaly always use the id translation function
in LL API calls.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
In preparation for QSPI DMA mode:
-Add a possibility to override driver by the HAL DMA. In that case
stream is set as busy and no configuration nor treatment is done.
In case of interrupt, flags clearing is let to HAL.
-Treat Half Transfer interrupt prior to Transfer Complete for the
cases were both IRQ are both raised at the time IRQ handler is called
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
