/* * Copyright 2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ #include / { cpus { /delete-node/ cpu@4; /delete-node/ cpu@5; /delete-node/ cpu@6; /delete-node/ cpu@7; }; soc { stm0: stm@76200000 { compatible = "nxp,s32-sys-timer"; reg = <0x76200000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>; status = "disabled"; }; stm1: stm@76210000 { compatible = "nxp,s32-sys-timer"; reg = <0x76210000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>; status = "disabled"; }; stm2: stm@76020000 { compatible = "nxp,s32-sys-timer"; reg = <0x76020000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>; status = "disabled"; }; stm3: stm@76030000 { compatible = "nxp,s32-sys-timer"; reg = <0x76030000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>; status = "disabled"; }; swt0: watchdog@76000000 { compatible = "nxp,s32-swt"; reg = <0x76000000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_FIRC_CLK>; status = "disabled"; }; swt1: watchdog@76010000 { compatible = "nxp,s32-swt"; reg = <0x76010000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_FIRC_CLK>; status = "disabled"; }; swt2: watchdog@76220000 { compatible = "nxp,s32-swt"; reg = <0x76220000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_FIRC_CLK>; status = "disabled"; }; swt3: watchdog@76230000 { compatible = "nxp,s32-swt"; reg = <0x76230000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_FIRC_CLK>; status = "disabled"; }; swt4: watchdog@76140000 { compatible = "nxp,s32-swt"; reg = <0x76140000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_FIRC_CLK>; status = "disabled"; }; pit0: pit@76150000 { compatible = "nxp,kinetis-pit"; reg = <0x76150000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_P0_REG_INTF_CLK>; max-load-value = <0x00ffffff>; status = "disabled"; }; }; };