d2b5ac20d1
In case of ARCv3 we have shared cache disabled after reset (in ARCv2 it was enabled by default). Let's enable it at early boot phase (if it's available in HW). Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
136 lines
3.2 KiB
C
136 lines
3.2 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Full C support initialization
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*
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*
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* Initialization of full C support: zero the .bss, copy the .data if XIP,
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* call z_cstart().
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*
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* Stack is available in this module, but not the global data/bss until their
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* initialization is performed.
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*/
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#include <zephyr/types.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/arch/arc/v2/aux_regs.h>
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#include <zephyr/arch/arc/cluster.h>
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#include <zephyr/kernel_structs.h>
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#include <kernel_internal.h>
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/* XXX - keep for future use in full-featured cache APIs */
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#if 0
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/**
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* @brief Disable the i-cache if present
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*
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* For those ARC CPUs that have a i-cache present,
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* invalidate the i-cache and then disable it.
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*/
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static void disable_icache(void)
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{
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unsigned int val;
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val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if i-cache is not present */
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}
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z_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
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__builtin_arc_nop();
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z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
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}
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/**
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* @brief Invalidate the data cache if present
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*
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* For those ARC CPUs that have a data cache present,
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* invalidate the data cache.
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*/
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static void invalidate_dcache(void)
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{
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unsigned int val;
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val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if d-cache is not present */
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}
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z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
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}
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#endif
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#ifdef CONFIG_ISA_ARCV3
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/* NOTE: it will be called from early C code - we must NOT use global / static variables in it! */
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static void arc_cluster_scm_enable(void)
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{
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unsigned int cluster_version;
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/* Check that we have cluster and its version is supported */
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cluster_version = z_arc_v2_aux_reg_read(_ARC_REG_CLN_BCR) & _ARC_CLN_BCR_VER_MAJOR_MASK;
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if (cluster_version < _ARC_REG_CLN_BCR_VER_MAJOR_ARCV3_MIN) {
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return;
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}
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/* Check that we have shared cache in cluster */
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if (!(z_arc_v2_aux_reg_read(_ARC_CLNR_BCR_0) & _ARC_CLNR_BCR_0_HAS_SCM)) {
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return;
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}
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/* Disable SCM, just in case. */
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arc_cln_write_reg_nolock(ARC_CLN_CACHE_STATUS, 0);
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/* Invalidate SCM before enabling. */
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arc_cln_write_reg_nolock(ARC_CLN_CACHE_CMD,
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ARC_CLN_CACHE_CMD_OP_REG_INV | ARC_CLN_CACHE_CMD_INCR);
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while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY)
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;
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arc_cln_write_reg_nolock(ARC_CLN_CACHE_STATUS, ARC_CLN_CACHE_STATUS_EN);
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}
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#endif /* CONFIG_ISA_ARCV3 */
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#ifdef __CCAC__
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extern char __device_states_start[];
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extern char __device_states_end[];
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/**
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* @brief Clear device_states section
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*
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* This routine clears the device_states section,
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* as MW compiler marks the section with NOLOAD flag.
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*/
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static void dev_state_zero(void)
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{
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z_early_memset(__device_states_start, 0, __device_states_end - __device_states_start);
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}
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#endif
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extern FUNC_NORETURN void z_cstart(void);
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/**
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*/
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void z_prep_c(void)
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{
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#ifdef CONFIG_ISA_ARCV3
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arc_cluster_scm_enable();
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#endif
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z_bss_zero();
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#ifdef __CCAC__
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dev_state_zero();
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#endif
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z_data_copy();
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z_cstart();
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CODE_UNREACHABLE;
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}
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