93a4287115
This commit adds implementation of GDB stub for 32-bit ARM. It has been tested only on the Zynq-7000 SoC and I would like to get any feedback from others. The stub still has these issues: - To implement single stepping, it uses instruction address mismatch breakpoint, as recommended in ARMv7 reference. The breakpoint control register is configured (the state control fields) for the "PL0, Supervisor and System modes only" option. Otherwise the breakpoint would also halt the processor in abort mode, in which the stub loop runs. Zephyr kernel runs in the system mode. This works well until the kernel enables interrupts, as interrupt handlers typically run in Supervisor mode. Single stepping therefore sometimes "catches" a handler instead of the next application instruction. I have not tried User mode, because Cortex-A SoCs do not appear to have the ARCH_HAS_USERSPACE flag. Cc: Michal Sojka <michal.sojka@cvut.cz> Signed-off-by: Marek Vedral <marek.vedral@gmail.com>
331 lines
11 KiB
Plaintext
331 lines
11 KiB
Plaintext
# ARM core configuration options
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# Copyright (c) 2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config CPU_CORTEX_M
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bool
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select CPU_CORTEX
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select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
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select HAS_CMSIS_CORE
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select HAS_FLASH_LOAD_OFFSET
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select ARCH_HAS_SINGLE_THREAD_SUPPORT
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select ARCH_HAS_THREAD_ABORT
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select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
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select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
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select ARCH_HAS_USERSPACE if ARM_MPU
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
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select ARCH_HAS_RAMFUNC_SUPPORT
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select ARCH_HAS_NESTED_EXCEPTION_DETECTION
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select SWAP_NONATOMIC
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select ARCH_HAS_EXTRA_EXCEPTION_INFO
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select ARCH_HAS_TIMING_FUNCTIONS if CPU_CORTEX_M_HAS_DWT
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select ARCH_SUPPORTS_ARCH_HW_INIT
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select ARCH_HAS_SUSPEND_TO_RAM
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select ARCH_HAS_CODE_DATA_RELOCATION
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select ARCH_SUPPORTS_ROM_START
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imply XIP
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help
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This option signifies the use of a CPU of the Cortex-M family.
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config CPU_AARCH32_CORTEX_R
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bool
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select CPU_CORTEX
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select HAS_CMSIS_CORE
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select ARCH_HAS_NESTED_EXCEPTION_DETECTION
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select HAS_FLASH_LOAD_OFFSET
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select ARCH_HAS_USERSPACE if ARM_MPU && !USE_SWITCH
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select ARCH_HAS_EXTRA_EXCEPTION_INFO if !USE_SWITCH
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select ARCH_HAS_CODE_DATA_RELOCATION
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
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select ARCH_SUPPORTS_ROM_START
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select USE_SWITCH_SUPPORTED
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help
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This option signifies the use of a CPU of the Cortex-R family.
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config ARM_ZIMAGE_HEADER
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bool "zImage Header"
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depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR
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help
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This option adds a zImage Header.
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config CPU_AARCH32_CORTEX_A
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bool
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select CPU_CORTEX
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select CPU_HAS_MMU
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select HAS_CMSIS_CORE
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select HAS_FLASH_LOAD_OFFSET
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select ARCH_HAS_EXTRA_EXCEPTION_INFO if !USE_SWITCH
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
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select USE_SWITCH_SUPPORTED
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# GDBSTUB has not yet been tested on Cortex M or R SoCs
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select ARCH_HAS_GDBSTUB
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# GDB on ARM needs the etxra registers
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select EXTRA_EXCEPTION_INFO if GDBSTUB
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help
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This option signifies the use of a CPU of the Cortex-A family.
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config GDBSTUB_BUF_SZ
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# GDB for ARM expects up to 18 4-byte plus 8 12-byte
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# registers - 336 HEX letters
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default 350 if GDBSTUB
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config ISA_THUMB2
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bool
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help
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From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
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Thumb-2 technology is the instruction set underlying the ARM Cortex
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architecture which provides enhanced levels of performance, energy
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efficiency, and code density for a wide range of embedded
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applications.
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Thumb-2 technology builds on the success of Thumb, the innovative
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high code density instruction set for ARM microprocessor cores, to
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increase the power of the ARM microprocessor core available to
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developers of low cost, high performance systems.
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The technology is backwards compatible with existing ARM and Thumb
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solutions, while significantly extending the features available to
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the Thumb instructions set. This allows more of the application to
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benefit from the best in class code density of Thumb.
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For performance optimized code Thumb-2 technology uses 31 percent
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less memory to reduce system cost, while providing up to 38 percent
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higher performance than existing high density code, which can be used
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to prolong battery-life or to enrich the product feature set. Thumb-2
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technology is featured in the processor, and in all ARMv7
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architecture-based processors.
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config ISA_ARM
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bool
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help
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From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
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A32 instructions, known as Arm instructions in pre-Armv8 architectures,
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are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
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are supported by both A-profile and R-profile architectures.
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A32 was traditionally used in applications requiring the highest
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performance, or for handling hardware exceptions such as interrupts and
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processor start-up. Much of its functionality was subsumed into T32 with
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the introduction of Thumb-2 technology.
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config ASSEMBLER_ISA_THUMB2
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bool
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default y if ISA_THUMB2 && !ISA_ARM
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depends on !ISA_ARM
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help
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This helper symbol specifies the default target instruction set for
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the assembler.
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When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the
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assembler must use the Thumb-2 instruction set.
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When both the Thumb-2 and ARM ISAs are supported (i.e. on Cortex-A
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and Cortex-R cores), the assembler must use the ARM instruction set
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because the architecture assembly code makes use of the ARM
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instructions.
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config COMPILER_ISA_THUMB2
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bool "Compile C/C++ functions using Thumb-2 instruction set"
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depends on ISA_THUMB2
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default y
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help
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This option configures the compiler to compile all C/C++ functions
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using the Thumb-2 instruction set.
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N.B. The scope of this symbol is not necessarily limited to the C and
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C++ languages; in fact, this symbol refers to all forms of
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"compiled" code.
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When an additional natively-compiled language support is added
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in the future, this symbol shall also specify the Thumb-2
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instruction set for that language.
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config NUM_IRQS
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int
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config STACK_ALIGN_DOUBLE_WORD
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bool "Align stacks on double-words (8 octets)"
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default y
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help
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This is needed to conform to AAPCS, the procedure call standard for
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the ARM. It wastes stack space. The option also enforces alignment
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of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
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Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
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on exception entry is enabled by default and it is not configurable.
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config RUNTIME_NMI
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bool "Attach an NMI handler at runtime"
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select REBOOT
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help
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The kernel provides a simple NMI handler that simply hangs in a tight
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loop if triggered. This fills the requirement that there must be an
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NMI handler installed when the CPU boots. If a custom handler is
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needed, enable this option and attach it via z_arm_nmi_set_handler().
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config PLATFORM_SPECIFIC_INIT
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bool "Platform (SOC) specific startup hook"
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help
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The platform specific initialization code (z_arm_platform_init) is
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executed at the beginning of the startup code (__start).
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config FAULT_DUMP
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int "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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config BUILTIN_STACK_GUARD
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bool "Thread Stack Guards based on built-in ARM stack limit checking"
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depends on CPU_CORTEX_M_HAS_SPLIM
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select THREAD_STACK_INFO
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help
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Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
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limit checking. The functionality must be supported by HW.
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config ARM_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
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select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
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help
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This option enables either:
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- The built-in Stack Pointer limit checking, or
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- the MPU-based stack guard
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to cause a system fatal error
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if the bounds of the current process stack are overflowed.
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The two stack guard options are mutually exclusive. The
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selection of the built-in Stack Pointer limit checking is
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prioritized over the MPU-based stack guard. The developer
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still has the option to manually select the MPU-based
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stack guard, if this is desired.
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config ARM_SECURE_FIRMWARE
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bool
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depends on ARMV8_M_SE
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default y if TRUSTED_EXECUTION_SECURE
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help
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This option indicates that we are building a Zephyr image that
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is intended to execute in Secure state. The option is only
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applicable to ARMv8-M MCUs that implement the Security Extension.
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This option enables Zephyr to include code that executes in
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Secure state, as well as to exclude code that is designed to
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execute only in Non-secure state.
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Code executing in Secure state has access to both the Secure
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and Non-Secure resources of the Cortex-M MCU.
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Code executing in Non-Secure state may trigger Secure Faults,
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if Secure MCU resources are accessed from the Non-Secure state.
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Secure Faults may only be handled by code executing in Secure
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state.
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config ARM_NONSECURE_FIRMWARE
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bool
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depends on !ARM_SECURE_FIRMWARE
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depends on ARMV8_M_SE
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default y if TRUSTED_EXECUTION_NONSECURE
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help
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This option indicates that we are building a Zephyr image that
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is intended to execute in Non-Secure state. Execution of this
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image is triggered by Secure firmware that executes in Secure
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state. The option is only applicable to ARMv8-M MCUs that
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implement the Security Extension.
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This option enables Zephyr to include code that executes in
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Non-Secure state only, as well as to exclude code that is
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designed to execute only in Secure state.
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Code executing in Non-Secure state has no access to Secure
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resources of the Cortex-M MCU, and, therefore, it shall avoid
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accessing them.
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config ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS
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bool "Allow secure function calls to be preempted"
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depends on ARM_NONSECURE_FIRMWARE
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help
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When enabled, this option indicates that preemptible Zephyr
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threads performing secure function calls, are allowed to be
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preempted. When disabled, the option indicates that such
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threads many not be context-switched-out while doing a Secure
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function call.
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config ARM_STORE_EXC_RETURN
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bool
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default y if CPU_CORTEX_M && (FPU_SHARING || ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS)
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help
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Store the EXC_RETURN value when switching threads.
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This is needed when switching between threads that differ in either
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FPU usage or security domain.
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choice
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prompt "Floating point ABI"
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default FP_HARDABI
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depends on FPU
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config FP_HARDABI
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bool "Floating point Hard ABI"
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help
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This option selects the Floating point ABI in which hardware floating
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point instructions are generated and uses FPU-specific calling
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conventions.
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config FP_SOFTABI
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bool "Floating point Soft ABI"
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help
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This option selects the Floating point ABI in which hardware floating
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point instructions are generated but soft-float calling conventions.
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endchoice
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config FP16
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bool "Half-precision floating point support"
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default y
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help
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This option enables the half-precision (16-bit) floating point support
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via the `__fp16` (both IEEE and ARM alternative formats) and the
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`_Float16` (defined by ISO/IEC TS 18661-3:2015) types.
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choice
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prompt "FP16 format"
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default FP16_IEEE
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depends on FP16
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config FP16_IEEE
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bool "FP16 IEEE format"
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help
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This option selects the IEEE 754-2008 format for FP16. This format can
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represent normalized values in the range of 2^(-14) to 65504. There are
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11 bits of significand precision, approximately 3 decimal digits.
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config FP16_ALT
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bool "FP16 ARM alternative format"
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help
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This option selects the ARM alternative format for FP16. This
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representation is similar to the IEEE 754-2008 format, but does not
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support infinites or NaNs. Instead, the range of exponents is extended,
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so that this format can represent normalized values in the range of
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2^(-14) to 131008.
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Please note that Clang doesn't support the ARM alternative format.
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endchoice
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rsource "cortex_m/Kconfig"
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rsource "cortex_a_r/Kconfig"
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rsource "mpu/Kconfig"
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rsource "mmu/Kconfig"
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