b1d2a8a9b6
Add binding, include header, and driver for NXP VREF IP block. NXP VREF is an internal voltage reference generator on some SOCs that fits well with the regulator API in zephyr. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
222 lines
5.8 KiB
C
222 lines
5.8 KiB
C
/*
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* Copyright 2023 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_vref
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#include <errno.h>
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#include <zephyr/drivers/regulator.h>
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#include <zephyr/dt-bindings/regulator/nxp_vref.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/linear_range.h>
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#include <zephyr/sys/util.h>
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#include <fsl_device_registers.h>
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static const struct linear_range utrim_range = LINEAR_RANGE_INIT(1000000, 100000U, 0x0U, 0xBU);
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struct regulator_nxp_vref_data {
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struct regulator_common_data common;
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};
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struct regulator_nxp_vref_config {
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struct regulator_common_config common;
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VREF_Type *base;
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uint8_t gnd_sel;
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uint16_t buf_start_delay;
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uint16_t bg_start_time;
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};
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static int regulator_nxp_vref_enable(const struct device *dev)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *const base = config->base;
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volatile uint32_t *const csr = &base->CSR;
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*csr |= VREF_CSR_LPBGEN_MASK | VREF_CSR_LPBG_BUF_EN_MASK;
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/* Wait for bandgap startup */
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k_busy_wait(config->bg_start_time);
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/* Enable high accuracy bandgap */
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*csr |= VREF_CSR_HCBGEN_MASK;
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/* Monitor until stable */
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while (!(*csr & VREF_CSR_VREFST_MASK))
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;
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/* Enable output buffer */
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*csr |= VREF_CSR_BUF21EN_MASK;
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return 0;
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}
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static int regulator_nxp_vref_disable(const struct device *dev)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *const base = config->base;
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/*
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* Disable HC Bandgap, LP Bandgap, and Buf21
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* to achieve "Off" mode of VREF
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*/
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base->CSR &= ~(VREF_CSR_BUF21EN_MASK | VREF_CSR_HCBGEN_MASK | VREF_CSR_LPBGEN_MASK);
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return 0;
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}
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static int regulator_nxp_vref_set_mode(const struct device *dev, regulator_mode_t mode)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *const base = config->base;
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uint32_t csr = base->CSR;
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if (mode == NXP_VREF_MODE_STANDBY) {
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csr &= ~VREF_CSR_REGEN_MASK &
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~VREF_CSR_CHOPEN_MASK &
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~VREF_CSR_HI_PWR_LV_MASK &
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~VREF_CSR_BUF21EN_MASK;
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} else if (mode == NXP_VREF_MODE_LOW_POWER) {
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csr &= ~VREF_CSR_REGEN_MASK &
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~VREF_CSR_CHOPEN_MASK &
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~VREF_CSR_HI_PWR_LV_MASK;
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csr |= VREF_CSR_BUF21EN_MASK;
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} else if (mode == NXP_VREF_MODE_HIGH_POWER) {
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csr &= ~VREF_CSR_REGEN_MASK &
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~VREF_CSR_CHOPEN_MASK;
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csr |= VREF_CSR_HI_PWR_LV_MASK &
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VREF_CSR_BUF21EN_MASK;
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} else if (mode == NXP_VREF_MODE_INTERNAL_REGULATOR) {
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csr |= VREF_CSR_REGEN_MASK &
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VREF_CSR_CHOPEN_MASK &
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VREF_CSR_HI_PWR_LV_MASK &
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VREF_CSR_BUF21EN_MASK;
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} else {
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return -EINVAL;
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}
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base->CSR = csr;
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k_busy_wait(config->buf_start_delay);
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return 0;
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}
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static int regulator_nxp_vref_get_mode(const struct device *dev, regulator_mode_t *mode)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *const base = config->base;
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uint32_t csr = base->CSR;
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/* Check bits to determine mode */
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if (csr & VREF_CSR_REGEN_MASK) {
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*mode = NXP_VREF_MODE_INTERNAL_REGULATOR;
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} else if (csr & VREF_CSR_HI_PWR_LV_MASK) {
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*mode = NXP_VREF_MODE_HIGH_POWER;
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} else if (csr & VREF_CSR_BUF21EN_MASK) {
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*mode = NXP_VREF_MODE_LOW_POWER;
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} else {
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*mode = NXP_VREF_MODE_STANDBY;
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}
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return 0;
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}
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static inline unsigned int regulator_nxp_vref_count_voltages(const struct device *dev)
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{
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return linear_range_values_count(&utrim_range);
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}
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static int regulator_nxp_vref_list_voltage(const struct device *dev,
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unsigned int idx, int32_t *volt_uv)
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{
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return linear_range_get_value(&utrim_range, idx, volt_uv);
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}
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static int regulator_nxp_vref_set_voltage(const struct device *dev,
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int32_t min_uv, int32_t max_uv)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *const base = config->base;
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uint16_t idx;
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int ret;
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ret = linear_range_get_win_index(&utrim_range, min_uv, max_uv, &idx);
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if (ret < 0) {
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return ret;
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}
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base->UTRIM &= ~VREF_UTRIM_TRIM2V1_MASK;
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base->UTRIM |= VREF_UTRIM_TRIM2V1_MASK & idx;
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return 0;
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}
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static int regulator_nxp_vref_get_voltage(const struct device *dev,
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int32_t *volt_uv)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *const base = config->base;
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uint16_t idx;
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int ret;
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/* Linear range index is the register value */
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idx = (base->UTRIM & VREF_UTRIM_TRIM2V1_MASK) >> VREF_UTRIM_TRIM2V1_SHIFT;
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ret = linear_range_get_value(&utrim_range, base->UTRIM, volt_uv);
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return ret;
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}
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static const struct regulator_driver_api api = {
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.enable = regulator_nxp_vref_enable,
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.disable = regulator_nxp_vref_disable,
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.set_mode = regulator_nxp_vref_set_mode,
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.get_mode = regulator_nxp_vref_get_mode,
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.set_voltage = regulator_nxp_vref_set_voltage,
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.get_voltage = regulator_nxp_vref_get_voltage,
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.list_voltage = regulator_nxp_vref_list_voltage,
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.count_voltages = regulator_nxp_vref_count_voltages,
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};
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static int regulator_nxp_vref_init(const struct device *dev)
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{
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const struct regulator_nxp_vref_config *config = dev->config;
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VREF_Type *base = config->base;
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int ret;
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regulator_common_data_init(dev);
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/* Select ground */
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base->CSR &= ~VREF_CSR_REFL_GRD_SEL_MASK;
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base->CSR |= config->gnd_sel;
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ret = regulator_nxp_vref_disable(dev);
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if (ret < 0) {
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return ret;
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}
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return regulator_common_init(dev, false);
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}
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#define REGULATOR_NXP_VREF_DEFINE(inst) \
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static struct regulator_nxp_vref_data data_##inst; \
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\
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static const struct regulator_nxp_vref_config config_##inst = { \
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.common = REGULATOR_DT_INST_COMMON_CONFIG_INIT(inst), \
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.base = (VREF_Type *) DT_INST_REG_ADDR(inst), \
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.gnd_sel = DT_INST_ENUM_IDX_OR(inst, nxp_ground_select, 0), \
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.buf_start_delay = DT_INST_PROP(inst, \
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nxp_buffer_startup_delay_us), \
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.bg_start_time = DT_INST_PROP(inst, \
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nxp_bandgap_startup_time_us), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, regulator_nxp_vref_init, NULL, &data_##inst,\
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&config_##inst, POST_KERNEL, \
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CONFIG_REGULATOR_NXP_VREF_INIT_PRIORITY, &api); \
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DT_INST_FOREACH_STATUS_OKAY(REGULATOR_NXP_VREF_DEFINE)
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