fcbf03a2dc
Unlike the remainder of the RT10xx series, the RT1011 SOC requires that the flash configuration block be placed at an offset of 0x400 bytes, instead of the start of the flash. Fixes #70090 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
190 lines
5.7 KiB
Plaintext
190 lines
5.7 KiB
Plaintext
# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_NXP_IMXRT
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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if SOC_FAMILY_NXP_IMXRT
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# Source series Kconfig files first, so SOCs
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# can override the defaults given here
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rsource "*/Kconfig"
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# Used for default value in FLASH_MCUX_FLEXSPI_XIP
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DT_CHOSEN_Z_FLASH := zephyr,flash
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DT_COMPAT_FLEXSPI := nxp,imx-flexspi
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# Macros to shorten Kconfig definitions
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DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
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DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
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config FLASH_MCUX_FLEXSPI_XIP
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bool "MCUX FlexSPI flash access with xip"
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default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
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select XIP
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help
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Allows for the soc to safely initialize the clocks for the
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FlexSpi when planning to execute code in FlexSpi Memory.
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if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
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choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
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prompt "FlexSPI drivers relocation target"
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default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
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help
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Select the location to run the FlexSPI drivers when using
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the flash API.
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config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
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bool "ITCM"
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select CODE_DATA_RELOCATION
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config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
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bool "RAM"
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select CODE_DATA_RELOCATION_SRAM
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endchoice
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config FLASH_MCUX_FLEXSPI_XIP_MEM
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string
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default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
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default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
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endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
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# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
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# should be set elsewhere, since the determination of which SOC core
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# requires the boot header is SOC specific.
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config NXP_IMXRT_BOOT_HEADER
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bool "Boot header"
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default y
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depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX)
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help
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Enable data structures required by the boot ROM to boot the
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application from an external flash device.
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if NXP_IMXRT_BOOT_HEADER
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choice BOOT_DEVICE
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prompt "Boot device"
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default BOOT_FLEXSPI_NOR
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config BOOT_FLEXSPI_NOR
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bool "FlexSPI serial NOR"
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depends on HAS_MCUX_FLEXSPI
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config BOOT_FLEXSPI_NAND
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bool "FlexSPI serial NAND"
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depends on HAS_MCUX_FLEXSPI
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config BOOT_SEMC_NOR
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bool "SEMC parallel NOR"
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depends on HAS_MCUX_SEMC
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config BOOT_SEMC_NAND
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bool "SEMC parallel NAND"
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depends on HAS_MCUX_SEMC
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endchoice # BOOT_DEVICE
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config FLEXSPI_CONFIG_BLOCK_OFFSET
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hex "FlexSPI config block offset"
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default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX || SOC_MIMXRT1011
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default 0x0 if BOOT_FLEXSPI_NOR
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help
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FlexSPI configuration block consists of parameters regarding specific
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flash devices including read command sequence, quad mode enablement
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sequence (optional), etc. The boot ROM expects FlexSPI configuration
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parameter to be presented in serial nor flash.
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config IMAGE_VECTOR_TABLE_OFFSET
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hex "Image vector table offset"
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default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
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default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
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help
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The Image Vector Table (IVT) provides the boot ROM with pointers to
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the application entry point and device configuration data. The boot
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ROM requires a fixed IVT offset for each type of boot device.
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config DEVICE_CONFIGURATION_DATA
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bool "Device configuration data"
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help
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Device configuration data (DCD) provides a sequence of commands to
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the boot ROM to initialize components such as an SDRAM. This is
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useful if your application expects components like SDRAM to be
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initialized at boot time.
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endif # NXP_IMXRT_BOOT_HEADER
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config NXP_IMX_EXTERNAL_SDRAM
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bool "Allow access to external SDRAM region"
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help
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Enable access to external SDRAM region managed by the SEMC. This
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setting should be enabled when the application uses SDRAM, or
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an MPU region will be defined to disable cached access to the
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SDRAM memory space.
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config NXP_IMX_RT_ROM_RAMLOADER
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depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER
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# Required so that debugger will load image to correct offset
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select BUILD_OUTPUT_HEX
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bool "Create output image that IMX RT ROM can load from FlexSPI to ram"
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help
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Builds an output image that the IMX RT BootROM can load from the
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FlexSPI boot device into RAM region. The image will be loaded
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from FLEXSPI into the region specified by `zephyr,flash` node.
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# Setup LMA adjustment if using the RAMLOADER feature of ROM
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FLASH_CHOSEN := zephyr,flash
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FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
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FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1)
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config BUILD_OUTPUT_ADJUST_LMA
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default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER
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config SECOND_CORE_MCUX
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bool "Dual core operation on the RT11xx series"
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depends on SOC_SERIES_IMXRT11XX
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help
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Indicates the second core will be enabled, and the part will run
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in dual core mode. Enables dual core operation on the RT11xx series,
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by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
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The M4 image will be loaded from flash into RAM based off a
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generated header specifying the VMA and LMA of each memory section
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to load
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config FLEXSPI_CONFIG_BLOCK_OFFSET
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hex
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default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
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if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
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config PM_MCUX_GPC
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bool "MCUX general power controller driver"
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config PM_MCUX_DCDC
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bool "MCUX dcdc converter module driver"
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config PM_MCUX_PMU
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bool "MCUX power management unit driver"
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config DCDC_VALUE
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hex "DCDC value for VDD_SOC"
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config INIT_ARM_PLL
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bool "Initialize ARM PLL"
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config INIT_VIDEO_PLL
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bool "Initialize Video PLL"
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config INIT_ENET_PLL
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bool
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help
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If y, the Ethernet PLL is initialized. Always enabled on e.g.
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MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
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for MIMXRT1021").
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endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
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endif # SOC_FAMILY_NXP_IMXRT
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