0187d60937
Improve initialization of the ADC. After initialization with the default values, the clock source of the ADC is asynchronous clock (ADACK) and clock divide ratio is 8. The minimum conversion clock frequency is 1MHz. Add clock divider selection and set default divide ratio to 1. That sets the conversion clock frequency to approximately 5MHz. Default configuration for the voltage reference is set to external pins V_REFH and V_REFL. Depending on the MCU configuration V_REFL may be connected to ground and V_REFH to VREF_OUT. Since Voltage Reference block is not supported, the ADC does not work properly on FRDM-KW41Z. Add voltage reference selection to fix it. Enable self-calibration function as recommeded in Reference Manual. Signed-off-by: Johann Fischer <j.fischer@phytec.de>
48 lines
890 B
Plaintext
48 lines
890 B
Plaintext
# Kconfig - ADC configuration options
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#
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# Copyright (c) 2015 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config ADC_MCUX_ADC16
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bool "MCUX ADC16 driver"
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depends on HAS_MCUX_ADC16
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help
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Enable the MCUX ADC16 driver.
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if ADC_MCUX_ADC16
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choice
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prompt "Clock Divide Selection"
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default ADC_MCUX_ADC16_CLK_DIV_RATIO_1
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config ADC_MCUX_ADC16_CLK_DIV_RATIO_1
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bool "Divide ratio is 1"
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config ADC_MCUX_ADC16_CLK_DIV_RATIO_2
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bool "Divide ratio is 2"
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config ADC_MCUX_ADC16_CLK_DIV_RATIO_4
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bool "Divide ratio is 4"
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config ADC_MCUX_ADC16_CLK_DIV_RATIO_8
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bool "Divide ratio is 8"
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endchoice
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choice
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prompt "Voltage Reference Selection"
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default ADC_MCUX_ADC16_VREF_DEFAULT
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config ADC_MCUX_ADC16_VREF_DEFAULT
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bool "Default voltage reference pair V_REFH and V_REFL"
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config ADC_MCUX_ADC16_VREF_ALTERNATE
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bool "Alternate reference pair"
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endchoice
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endif # ADC_MCUX_ADC16
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