0d4b46f51c
This change adds support for enabling ethernet MAC hardware checksum offloading for STM32H7 based devices. In Section 58.5.9 of the STM32H7 reference manual it mentions that the STM32H7 ethernet MAC supports a Checksum Offload Module (COE). I have tested the changes on my end where I enabled CONFIG_ETH_STM32_HW_CHECKSUM and ensured that an application that runs Zephyr on the STM32H7 can interoperate with a device with a completely different implementation. Also, I deliberately made the software not populate the IPv4 and UDP header checksum fields in their respective headers and the COE was able to populate the IPv4 and UDP header checksums. Given that CONFIG_ETH_STM32_HW_CHECKSUM is not enabled by default application developers have the option to either enable it or disable it. Signed-off-by: Chamira Perera <chamira.perera@audinate.com>
216 lines
5.9 KiB
Plaintext
216 lines
5.9 KiB
Plaintext
# STM32 HAL Ethernet driver configuration options
|
|
|
|
# Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
|
|
# Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
menuconfig ETH_STM32_HAL
|
|
bool "STM32 HAL Ethernet driver"
|
|
default y
|
|
depends on DT_HAS_ST_STM32_ETHERNET_ENABLED
|
|
select USE_STM32_HAL_ETH
|
|
select NOCACHE_MEMORY if SOC_SERIES_STM32H7X && CPU_CORTEX_M7
|
|
select HWINFO
|
|
imply CRC
|
|
help
|
|
Enable STM32 HAL based Ethernet driver. It is available for
|
|
all Ethernet enabled variants of the F2, F4, F7 and H7 series.
|
|
|
|
if ETH_STM32_HAL
|
|
|
|
choice ETH_STM32_HAL_API_VERSION
|
|
prompt "STM32Cube HAL Ethernet version"
|
|
|
|
config ETH_STM32_HAL_API_V2
|
|
bool "Use new HAL driver"
|
|
depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
|
|
help
|
|
Use the new HAL driver instead of the legacy one.
|
|
|
|
config ETH_STM32_HAL_API_V1
|
|
bool "Use new HAL driver"
|
|
depends on !SOC_SERIES_STM32H5X
|
|
select DEPRECATED if SOC_SERIES_STM32H7X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
|
|
help
|
|
Driver version based on legacy HAL version. Deprecated unless using STM32F2 series.
|
|
|
|
endchoice
|
|
|
|
config ETH_STM32_HAL_RX_THREAD_STACK_SIZE
|
|
int "RX thread stack size"
|
|
default 1500
|
|
help
|
|
RX thread stack size
|
|
|
|
config ETH_STM32_HAL_RX_THREAD_PRIO
|
|
int "RX thread priority"
|
|
default 2
|
|
help
|
|
RX thread priority
|
|
|
|
config ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER
|
|
bool "Use DTCM for DMA buffers"
|
|
default y
|
|
depends on SOC_SERIES_STM32F7X
|
|
help
|
|
When this option is activated, the buffers for DMA transfer are
|
|
moved from SRAM to the DTCM (Data Tightly Coupled Memory).
|
|
|
|
config ETH_STM32_HAL_PHY_ADDRESS
|
|
int "Phy address"
|
|
default 0
|
|
help
|
|
The phy address to use.
|
|
|
|
choice
|
|
prompt "Mac address definition method"
|
|
optional
|
|
help
|
|
The driver supports 2 methods to define 3 last bytes of MAC address
|
|
1. Statically defined by user
|
|
2. Generated dynamically at each boot
|
|
|
|
Note: Configuring this methods using Kconfig is now deprecated in favor
|
|
of device tree based configuration.
|
|
|
|
config ETH_STM32_HAL_RANDOM_MAC
|
|
bool "Random MAC address (DEPRECATED)"
|
|
depends on ENTROPY_GENERATOR
|
|
select DEPRECATED
|
|
help
|
|
Generate a random MAC address dynamically.
|
|
Deprecated in favor of device tree property "zephyr,random-mac-address"
|
|
|
|
config ETH_STM32_HAL_USER_STATIC_MAC
|
|
bool "User defined MAC address (DEPRECATED)"
|
|
select DEPRECATED
|
|
help
|
|
3 last bytes of MAC address are defined by user thanks to
|
|
ETH_STM32_HAL_MAC3, ETH_STM32_HAL_MAC4 and ETH_STM32_HAL_MAC5.
|
|
Deprecated in favor of device tree property "local-mac-address"
|
|
|
|
endchoice
|
|
|
|
if ETH_STM32_HAL_USER_STATIC_MAC
|
|
|
|
config ETH_STM32_HAL_MAC3
|
|
hex "MAC Address Byte 3 (DEPRECATED)"
|
|
default 0
|
|
range 0 0xff
|
|
help
|
|
This is the byte 3 of the MAC address.
|
|
|
|
config ETH_STM32_HAL_MAC4
|
|
hex "MAC Address Byte 4 (DEPRECATED)"
|
|
default 0
|
|
range 0 0xff
|
|
help
|
|
This is the byte 4 of the MAC address.
|
|
|
|
config ETH_STM32_HAL_MAC5
|
|
hex "MAC Address Byte 5 (DEPRECATED)"
|
|
default 0
|
|
range 0 0xff
|
|
help
|
|
This is the byte 5 of the MAC address.
|
|
|
|
endif # ETH_STM32_HAL_USER_STATIC_MAC
|
|
|
|
config ETH_STM32_HAL_MII
|
|
bool "Use MII interface"
|
|
help
|
|
Use the MII physical interface instead of RMII.
|
|
|
|
config ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS
|
|
int "Carrier check timeout period (ms)"
|
|
default 500
|
|
range 100 30000
|
|
help
|
|
Set the RX idle timeout period in milliseconds after which the
|
|
PHY's carrier status is re-evaluated.
|
|
|
|
config ETH_STM32_AUTO_NEGOTIATION_ENABLE
|
|
bool "Autonegotiation mode"
|
|
default y
|
|
help
|
|
Enable this if using autonegotiation
|
|
|
|
config ETH_STM32_HW_CHECKSUM
|
|
bool "Use TX and RX hardware checksum"
|
|
depends on !SOC_SERIES_STM32H5X
|
|
help
|
|
Enable receive and transmit checksum offload to enhance throughput
|
|
performances.
|
|
See reference manual for more information on this feature.
|
|
|
|
if !ETH_STM32_AUTO_NEGOTIATION_ENABLE
|
|
|
|
config ETH_STM32_SPEED_10M
|
|
bool "Set speed to 10 Mbps when autonegotiation is disabled"
|
|
help
|
|
Set this if using 10 Mbps and when autonegotiation is disabled, otherwise speed
|
|
is 100 Mbps
|
|
|
|
config ETH_STM32_MODE_HALFDUPLEX
|
|
bool "Half duplex mode"
|
|
help
|
|
Set this if using half duplex when autonegotiation is disabled otherwise
|
|
duplex mode is full duplex
|
|
|
|
endif # !ETH_STM32_AUTO_NEGOTIATION_ENABLE
|
|
|
|
if SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X
|
|
|
|
config PTP_CLOCK_STM32_HAL
|
|
bool "STM32 HAL PTP clock driver support"
|
|
default y
|
|
depends on PTP_CLOCK || NET_L2_PTP
|
|
help
|
|
Enable STM32 PTP clock support.
|
|
|
|
config ETH_STM32_HAL_PTP_CLOCK_SRC_HZ
|
|
int "Frequency of the clock source for the PTP timer"
|
|
default 50000000
|
|
depends on PTP_CLOCK_STM32_HAL
|
|
help
|
|
Set the frequency in Hz sourced to the PTP timer.
|
|
If the value is set properly, the timer will be accurate.
|
|
|
|
config ETH_STM32_HAL_PTP_CLOCK_ADJ_MIN_PCT
|
|
int "Lower bound of clock frequency adjustment (in percent)"
|
|
default 90
|
|
depends on PTP_CLOCK_STM32_HAL
|
|
help
|
|
Specifies lower bound of PTP clock rate adjustment.
|
|
|
|
config ETH_STM32_HAL_PTP_CLOCK_ADJ_MAX_PCT
|
|
int "Upper bound of clock frequency adjustment (in percent)"
|
|
default 110
|
|
depends on PTP_CLOCK_STM32_HAL
|
|
help
|
|
Specifies upper bound of PTP clock rate adjustment.
|
|
|
|
config ETH_STM32_HAL_PTP_CLOCK_INIT_PRIO
|
|
int
|
|
default 85
|
|
depends on PTP_CLOCK_STM32_HAL
|
|
help
|
|
STM32 PTP Clock initialization priority level. There is
|
|
a dependency from the network stack that this device
|
|
initializes before network stack (NET_INIT_PRIO).
|
|
|
|
endif # SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X
|
|
|
|
config ETH_STM32_MULTICAST_FILTER
|
|
bool "Multicast hash filter support"
|
|
help
|
|
Enable support for multicast hash filtering in the MAC.
|
|
Once enabled the ethernet MAC performs imperfect filtering
|
|
based on a computed hash of the destination MAC address of
|
|
the multicast address. Only multicast with the computed
|
|
hash set in the multicast table will be received and all
|
|
other multicast is dropped by the MAC. If disabled then all
|
|
multicast is received by the MAC.
|
|
|
|
endif # ETH_STM32_HAL
|