a417392f76
In sys_clock_set_timeout(), input "ticks" is used to compute next timeout point, Ambiq's STimer API used to sets next timeout has input parameter as ui32Delta, which inside the API is using "this value to add to the STimer counter and load into the comparator register" according to its spec, thus the this delta clock is almost equivalent to input "ticks"'s concept, and is not related to last_count, it should be computed directly from input "ticks". This correction fixes the test case failure at zephyr\tests\kernel\tickless\tickless_concept. Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
146 lines
3.3 KiB
C
146 lines
3.3 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_stimer
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/**
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* @file
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* @brief Ambiq Apollo STIMER-based sys_clock driver
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*
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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/* ambiq-sdk includes */
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#include <am_mcu_apollo.h>
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#define COUNTER_MAX UINT32_MAX
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#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
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#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
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#define MIN_DELAY 1
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#define TIMER_IRQ (DT_INST_IRQN(0))
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#if defined(CONFIG_TEST)
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const int32_t z_sys_timer_irq_for_test = TIMER_IRQ;
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#endif
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/* Value of STIMER counter when the previous kernel tick was announced */
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static atomic_t g_last_count;
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/* Spinlock to sync between Compare ISR and update of Compare register */
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static struct k_spinlock g_lock;
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static void stimer_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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uint32_t irq_status = am_hal_stimer_int_status_get(false);
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if (irq_status & AM_HAL_STIMER_INT_COMPAREA) {
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am_hal_stimer_int_clear(AM_HAL_STIMER_INT_COMPAREA);
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k_spinlock_key_t key = k_spin_lock(&g_lock);
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uint32_t now = am_hal_stimer_counter_get();
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uint32_t dticks = (uint32_t)((now - g_last_count) / CYC_PER_TICK);
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g_last_count += dticks * CYC_PER_TICK;
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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uint32_t next = g_last_count + CYC_PER_TICK;
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if ((int32_t)(next - now) < MIN_DELAY) {
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next += CYC_PER_TICK;
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}
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am_hal_stimer_compare_delta_set(0, next - g_last_count);
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}
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k_spin_unlock(&g_lock, key);
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sys_clock_announce(dticks);
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}
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return;
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}
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if (ticks == K_TICKS_FOREVER) {
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return;
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}
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ticks = MIN(MAX_TICKS, ticks);
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/* If tick is 0, set delta cyc to MIN_DELAY to trigger tick isr asap */
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uint32_t cyc = MAX(ticks * CYC_PER_TICK, MIN_DELAY);
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k_spinlock_key_t key = k_spin_lock(&g_lock);
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am_hal_stimer_compare_delta_set(0, cyc);
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k_spin_unlock(&g_lock, key);
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}
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uint32_t sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&g_lock);
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uint32_t ret = (am_hal_stimer_counter_get()
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- g_last_count) / CYC_PER_TICK;
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k_spin_unlock(&g_lock, key);
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return ret;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return am_hal_stimer_counter_get();
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}
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static int stimer_init(void)
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{
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uint32_t oldCfg;
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k_spinlock_key_t key = k_spin_lock(&g_lock);
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oldCfg = am_hal_stimer_config(AM_HAL_STIMER_CFG_FREEZE);
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am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | STIMER_STCFG_CLKSEL_Msk))
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| AM_HAL_STIMER_XTAL_32KHZ
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| AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
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g_last_count = am_hal_stimer_counter_get();
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k_spin_unlock(&g_lock, key);
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NVIC_ClearPendingIRQ(TIMER_IRQ);
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IRQ_CONNECT(TIMER_IRQ, 0, stimer_isr, 0, 0);
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irq_enable(TIMER_IRQ);
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am_hal_stimer_int_enable(AM_HAL_STIMER_INT_COMPAREA);
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/* Start timer with period CYC_PER_TICK if tickless is not enabled */
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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am_hal_stimer_compare_delta_set(0, CYC_PER_TICK);
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}
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return 0;
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}
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SYS_INIT(stimer_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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