826d67af91
Using the 8 base clock cycles per bit period setting (instead of 16) reduces the uart baud rate error when using a 12MHz crystal (found on many RA Microcontroller development kits boards). This setting also slightly reduces the error when using the internal 48MHz oscillator, used by the Arduino UNO R4 Minima board currently support by Zephyr. Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
731 lines
22 KiB
C
731 lines
22 KiB
C
/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra_uart_sci
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ra_uart_sci, CONFIG_UART_LOG_LEVEL);
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enum {
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UART_RA_INT_RXI,
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UART_RA_INT_TXI,
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UART_RA_INT_ERI,
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NUM_OF_UART_RA_INT,
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};
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struct uart_ra_cfg {
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mem_addr_t regs;
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const struct device *clock_dev;
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clock_control_subsys_t clock_id;
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const struct pinctrl_dev_config *pcfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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int (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct uart_ra_data {
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struct uart_config current_config;
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uint32_t clk_rate;
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struct k_spinlock lock;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uint32_t irqn[NUM_OF_UART_RA_INT];
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uart_irq_callback_user_data_t callback;
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void *cb_data;
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#endif
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};
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#define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS))
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/* Registers */
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#define SMR 0x00 /*!< Serial Mode Register */
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#define BRR 0x01 /*!< Bit Rate Register */
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#define SCR 0x02 /*!< Serial Control Register */
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#define TDR 0x03 /*!< Transmit Data Register */
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#define SSR 0x04 /*!< Serial Status Register */
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#define RDR 0x05 /*!< Receive Data Register */
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#define SEMR 0x07 /*!< Serial Extended Mode Register */
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#define MDDR 0x12 /*!< Modulation Duty Register */
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#define LSR 0x18 /*!< Line Status Register */
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/*
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* SMR (Serial Mode Register)
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*
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* - CKS[0..2]: Clock Select
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* - MP[2..3]: Multi-Processor Mode(Valid only in asynchronous mode)
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* - STOP[3..4]: Stop Bit Length(Valid only in asynchronous mode)
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* - PM[4..5]: Parity Mode (Valid only when the PE bit is 1)
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* - PE[5..6]: Parity Enable(Valid only in asynchronous mode)
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* - CHR[6..7]: Character Length(Valid only in asynchronous mode)
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* - CM[7..8]: Communication Mode
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*/
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#define SMR_CKS_POS (0)
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#define SMR_CKS_LEN (2)
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#define SMR_MP_POS (2)
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#define SMR_MP_LEN (1)
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#define SMR_STOP_POS (3)
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#define SMR_STOP_LEN (1)
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#define SMR_PM_POS (4)
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#define SMR_PM_LEN (1)
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#define SMR_PE_POS (5)
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#define SMR_PE_LEN (1)
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#define SMR_CHR_POS (6)
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#define SMR_CHR_LEN (1)
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#define SMR_CM_POS (7)
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#define SMR_CM_LEN (1)
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/**
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* SCR (Serial Control Register)
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*
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* - CKE[0..2]: Clock Enable
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* - TEIE[2..3]: Transmit End Interrupt Enable
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* - MPIE[3..4]: Multi-Processor Interrupt Enable (Valid in asynchronous
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* - RE[4..5]: Receive Enable
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* - TE[5..6]: Transmit Enable
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* - RIE[6..7]: Receive Interrupt Enable
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* - TIE[7..8]: Transmit Interrupt Enable
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*/
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#define SCR_CKE_POS (0)
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#define SCR_CKE_LEN (2)
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#define SCR_TEIE_POS (2)
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#define SCR_TEIE_LEN (1)
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#define SCR_MPIE_POS (3)
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#define SCR_MPIE_LEN (1)
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#define SCR_RE_POS (4)
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#define SCR_RE_LEN (1)
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#define SCR_TE_POS (5)
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#define SCR_TE_LEN (1)
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#define SCR_RIE_POS (6)
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#define SCR_RIE_LEN (1)
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#define SCR_TIE_POS (7)
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#define SCR_TIE_LEN (1)
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/**
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* SSR (Serial Status Register)
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*
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* - MPBT[0..1]: Multi-Processor Bit Transfer
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* - MPB[1..2]: Multi-Processor
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* - TEND[2..3]: Transmit End Flag
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* - PER[3..4]: Parity Error Flag
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* - FER[4..5]: Framing Error Flag
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* - ORER[5..6]: Overrun Error Flag
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* - RDRF[6..7]: Receive Data Full Flag
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* - TDRE[7..8]: Transmit Data Empty Flag
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*/
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#define SSR_MPBT_POS (0)
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#define SSR_MPBT_LEN (1)
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#define SSR_MPB_POS (1)
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#define SSR_MPB_LEN (1)
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#define SSR_TEND_POS (2)
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#define SSR_TEND_LEN (1)
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#define SSR_PER_POS (3)
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#define SSR_PER_LEN (1)
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#define SSR_FER_POS (4)
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#define SSR_FER_LEN (1)
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#define SSR_ORER_POS (5)
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#define SSR_ORER_LEN (1)
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#define SSR_RDRF_POS (6)
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#define SSR_RDRF_LEN (1)
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#define SSR_TDRE_POS (7)
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#define SSR_TDRE_LEN (1)
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/**
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* SEMR (Serial Extended Mode Register)
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*
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* - ACS0[0..1]: Asynchronous Mode Clock Source Select
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* - PADIS[1..2]: Preamble function Disable
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* - BRME[2..3]: Bit Rate Modulation Enable
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* - ABCSE[3..4]: Asynchronous Mode Extended Base Clock Select
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* - ABCS[4..5]: Asynchronous Mode Base Clock Select
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* - NFEN[5..6]: Digital Noise Filter Function Enable
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* - BGDM[6..7]: Baud Rate Generator Double-Speed Mode Select
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* - RXDESEL[7..8]: Asynchronous Start Bit Edge Detection Select
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*/
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#define SEMR_ACS0_POS (0)
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#define SEMR_ACS0_LEN (1)
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#define SEMR_PADIS_POS (1)
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#define SEMR_PADIS_LEN (1)
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#define SEMR_BRME_POS (2)
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#define SEMR_BRME_LEN (1)
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#define SEMR_ABCSE_POS (3)
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#define SEMR_ABCSE_LEN (1)
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#define SEMR_ABCS_POS (4)
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#define SEMR_ABCS_LEN (1)
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#define SEMR_NFEN_POS (5)
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#define SEMR_NFEN_LEN (1)
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#define SEMR_BGDM_POS (6)
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#define SEMR_BGDM_LEN (1)
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#define SEMR_RXDESEL_POS (7)
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#define SEMR_RXDESEL_LEN (1)
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/**
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* LSR (Line Status Register)
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*
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* - ORER[0..1]: Overrun Error Flag
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* - FNUM[2..7]: Framing Error Count
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* - PNUM[8..13]: Parity Error Count
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*/
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#define LSR_ORER_POS (0)
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#define LSR_ORER_LEN (1)
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#define LSR_FNUM_POS (2)
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#define LSR_FNUM_LEN (5)
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#define LSR_PNUM_POS (8)
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#define LSR_PNUM_LEN (5)
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static uint8_t uart_ra_read_8(const struct device *dev, uint32_t offs)
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{
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const struct uart_ra_cfg *config = dev->config;
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return sys_read8(config->regs + offs);
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}
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static void uart_ra_write_8(const struct device *dev, uint32_t offs, uint8_t value)
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{
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const struct uart_ra_cfg *config = dev->config;
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sys_write8(value, config->regs + offs);
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}
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static uint16_t uart_ra_read_16(const struct device *dev, uint32_t offs)
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{
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const struct uart_ra_cfg *config = dev->config;
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return sys_read16(config->regs + offs);
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}
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static void uart_ra_write_16(const struct device *dev, uint32_t offs, uint16_t value)
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{
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const struct uart_ra_cfg *config = dev->config;
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sys_write16(value, config->regs + offs);
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}
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static void uart_ra_set_baudrate(const struct device *dev, uint32_t baud_rate)
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{
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struct uart_ra_data *data = dev->data;
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uint8_t reg_val;
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reg_val = uart_ra_read_8(dev, SEMR);
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reg_val |= (REG_MASK(SEMR_BGDM) | REG_MASK(SEMR_ABCS));
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reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE));
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uart_ra_write_8(dev, SEMR, reg_val);
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reg_val = (data->clk_rate / (8 * data->current_config.baudrate)) - 1;
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uart_ra_write_8(dev, BRR, reg_val);
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}
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static int uart_ra_poll_in(const struct device *dev, unsigned char *p_char)
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{
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struct uart_ra_data *data = dev->data;
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int ret = 0;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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/* If interrupts are enabled, return -EINVAL */
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if ((uart_ra_read_8(dev, SCR) & REG_MASK(SCR_RIE))) {
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ret = -EINVAL;
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goto unlock;
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}
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if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
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ret = -1;
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goto unlock;
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}
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*p_char = uart_ra_read_8(dev, RDR);
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unlock:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static void uart_ra_poll_out(const struct device *dev, unsigned char out_char)
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{
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struct uart_ra_data *data = dev->data;
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uint8_t reg_val;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
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!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
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;
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}
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/* If interrupts are enabled, temporarily disable them */
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reg_val = uart_ra_read_8(dev, SCR);
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uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE));
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uart_ra_write_8(dev, TDR, out_char);
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while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
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!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
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;
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}
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uart_ra_write_8(dev, SCR, reg_val);
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k_spin_unlock(&data->lock, key);
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}
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static int uart_ra_err_check(const struct device *dev)
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{
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struct uart_ra_data *data = dev->data;
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uint8_t reg_val;
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int errors = 0;
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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reg_val = uart_ra_read_8(dev, SSR);
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if (reg_val & REG_MASK(SSR_PER)) {
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errors |= UART_ERROR_PARITY;
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}
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if (reg_val & REG_MASK(SSR_FER)) {
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errors |= UART_ERROR_FRAMING;
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}
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if (reg_val & REG_MASK(SSR_ORER)) {
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errors |= UART_ERROR_OVERRUN;
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}
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reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER));
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uart_ra_write_8(dev, SSR, reg_val);
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k_spin_unlock(&data->lock, key);
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return errors;
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}
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static int uart_ra_configure(const struct device *dev, const struct uart_config *cfg)
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{
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struct uart_ra_data *data = dev->data;
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uint16_t reg_val;
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k_spinlock_key_t key;
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if (cfg->parity != UART_CFG_PARITY_NONE || cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
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cfg->data_bits != UART_CFG_DATA_BITS_8 || cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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/* Disable Transmit and Receive */
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val &= ~(REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
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uart_ra_write_8(dev, SCR, reg_val);
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/* Resetting Errors Registers */
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reg_val = uart_ra_read_8(dev, SSR);
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reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER) |
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REG_MASK(SSR_RDRF) | REG_MASK(SSR_TDRE));
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uart_ra_write_8(dev, SSR, reg_val);
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reg_val = uart_ra_read_16(dev, LSR);
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reg_val &= ~(REG_MASK(LSR_ORER));
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uart_ra_write_16(dev, LSR, reg_val);
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/* Select internal clock */
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val &= ~(REG_MASK(SCR_CKE));
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uart_ra_write_8(dev, SCR, reg_val);
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/* Serial Configuration (8N1) & Clock divider selection */
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reg_val = uart_ra_read_8(dev, SMR);
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reg_val &= ~(REG_MASK(SMR_CM) | REG_MASK(SMR_CHR) | REG_MASK(SMR_PE) | REG_MASK(SMR_PM) |
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REG_MASK(SMR_STOP) | REG_MASK(SMR_CKS));
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uart_ra_write_8(dev, SMR, reg_val);
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/* Set baudrate */
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uart_ra_set_baudrate(dev, cfg->baudrate);
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/* Enable Transmit & Receive + disable Interrupts */
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val |= (REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
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reg_val &=
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~(REG_MASK(SCR_TIE) | REG_MASK(SCR_RIE) | REG_MASK(SCR_MPIE) | REG_MASK(SCR_TEIE));
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uart_ra_write_8(dev, SCR, reg_val);
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data->current_config = *cfg;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int uart_ra_config_get(const struct device *dev, struct uart_config *cfg)
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{
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struct uart_ra_data *data = dev->data;
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*cfg = data->current_config;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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static int uart_ra_init(const struct device *dev)
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{
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const struct uart_ra_cfg *config = dev->config;
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struct uart_ra_data *data = dev->data;
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int ret;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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if (!device_is_ready(config->clock_dev)) {
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return -ENODEV;
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}
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ret = clock_control_on(config->clock_dev, config->clock_id);
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if (ret < 0) {
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return ret;
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}
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ret = clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_rate);
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if (ret < 0) {
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return ret;
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}
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ret = uart_ra_configure(dev, &data->current_config);
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if (ret != 0) {
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return ret;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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ret = config->irq_config_func(dev);
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if (ret != 0) {
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return ret;
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static bool uart_ra_irq_is_enabled(const struct device *dev, uint32_t irq)
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{
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return uart_ra_read_8(dev, SCR) & irq;
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}
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static int uart_ra_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
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{
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struct uart_ra_data *data = dev->data;
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uint8_t reg_val;
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k_spinlock_key_t key;
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if (len <= 0 || tx_data == NULL) {
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return 0;
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}
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key = k_spin_lock(&data->lock);
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reg_val = uart_ra_read_8(dev, SCR);
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reg_val &= ~(REG_MASK(SCR_TIE));
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uart_ra_write_8(dev, SCR, reg_val);
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uart_ra_write_8(dev, TDR, tx_data[0]);
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reg_val |= REG_MASK(SCR_TIE);
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uart_ra_write_8(dev, SCR, reg_val);
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k_spin_unlock(&data->lock, key);
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return 1;
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}
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static int uart_ra_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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uint8_t data;
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if (size <= 0) {
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return 0;
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}
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if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
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return 0;
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}
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data = uart_ra_read_8(dev, RDR);
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if (rx_data) {
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rx_data[0] = data;
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}
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return 1;
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}
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static void uart_ra_irq_tx_enable(const struct device *dev)
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{
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struct uart_ra_data *data = dev->data;
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k_spinlock_key_t key;
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uint16_t reg_val;
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|
|
|
key = k_spin_lock(&data->lock);
|
|
|
|
reg_val = uart_ra_read_8(dev, SCR);
|
|
reg_val |= (REG_MASK(SCR_TIE));
|
|
uart_ra_write_8(dev, SCR, reg_val);
|
|
|
|
irq_enable(data->irqn[UART_RA_INT_TXI]);
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static void uart_ra_irq_tx_disable(const struct device *dev)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
k_spinlock_key_t key;
|
|
uint16_t reg_val;
|
|
|
|
key = k_spin_lock(&data->lock);
|
|
|
|
reg_val = uart_ra_read_8(dev, SCR);
|
|
reg_val &= ~(REG_MASK(SCR_TIE));
|
|
uart_ra_write_8(dev, SCR, reg_val);
|
|
|
|
irq_disable(data->irqn[UART_RA_INT_TXI]);
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static int uart_ra_irq_tx_ready(const struct device *dev)
|
|
{
|
|
const uint8_t reg_val = uart_ra_read_8(dev, SSR);
|
|
const uint8_t mask = REG_MASK(SSR_TEND) & REG_MASK(SSR_TDRE);
|
|
|
|
return (reg_val & mask) == mask;
|
|
}
|
|
|
|
static void uart_ra_irq_rx_enable(const struct device *dev)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
k_spinlock_key_t key;
|
|
uint16_t reg_val;
|
|
|
|
key = k_spin_lock(&data->lock);
|
|
|
|
reg_val = uart_ra_read_8(dev, SCR);
|
|
reg_val |= REG_MASK(SCR_RIE);
|
|
uart_ra_write_8(dev, SCR, reg_val);
|
|
|
|
irq_enable(data->irqn[UART_RA_INT_RXI]);
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static void uart_ra_irq_rx_disable(const struct device *dev)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
k_spinlock_key_t key;
|
|
uint16_t reg_val;
|
|
|
|
key = k_spin_lock(&data->lock);
|
|
|
|
reg_val = uart_ra_read_8(dev, SCR);
|
|
reg_val &= ~REG_MASK(SCR_RIE);
|
|
uart_ra_write_8(dev, SCR, reg_val);
|
|
|
|
irq_disable(data->irqn[UART_RA_INT_RXI]);
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static int uart_ra_irq_rx_ready(const struct device *dev)
|
|
{
|
|
return !!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF));
|
|
}
|
|
|
|
static void uart_ra_irq_err_enable(const struct device *dev)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
irq_enable(data->irqn[UART_RA_INT_ERI]);
|
|
}
|
|
|
|
static void uart_ra_irq_err_disable(const struct device *dev)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
irq_disable(data->irqn[UART_RA_INT_ERI]);
|
|
}
|
|
|
|
static int uart_ra_irq_is_pending(const struct device *dev)
|
|
{
|
|
return (uart_ra_irq_rx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_RIE))) ||
|
|
(uart_ra_irq_tx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_TIE)));
|
|
}
|
|
|
|
static int uart_ra_irq_update(const struct device *dev)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
static void uart_ra_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
|
|
void *cb_data)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
data->callback = cb;
|
|
data->cb_data = cb_data;
|
|
}
|
|
|
|
/**
|
|
* @brief Interrupt service routine.
|
|
*
|
|
* This simply calls the callback function, if one exists.
|
|
*
|
|
* @param arg Argument to ISR.
|
|
*/
|
|
static inline void uart_ra_isr(const struct device *dev)
|
|
{
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
if (data->callback) {
|
|
data->callback(dev, data->cb_data);
|
|
}
|
|
}
|
|
|
|
static void uart_ra_isr_rxi(const void *param)
|
|
{
|
|
const struct device *dev = param;
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
uart_ra_isr(dev);
|
|
ra_icu_clear_int_flag(data->irqn[UART_RA_INT_RXI]);
|
|
}
|
|
|
|
static void uart_ra_isr_txi(const void *param)
|
|
{
|
|
const struct device *dev = param;
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
uart_ra_isr(dev);
|
|
ra_icu_clear_int_flag(data->irqn[UART_RA_INT_TXI]);
|
|
}
|
|
|
|
static void uart_ra_isr_eri(const void *param)
|
|
{
|
|
const struct device *dev = param;
|
|
struct uart_ra_data *data = dev->data;
|
|
|
|
uart_ra_isr(dev);
|
|
ra_icu_clear_int_flag(data->irqn[UART_RA_INT_ERI]);
|
|
}
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
static const struct uart_driver_api uart_ra_driver_api = {
|
|
.poll_in = uart_ra_poll_in,
|
|
.poll_out = uart_ra_poll_out,
|
|
.err_check = uart_ra_err_check,
|
|
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
|
|
.configure = uart_ra_configure,
|
|
.config_get = uart_ra_config_get,
|
|
#endif
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.fifo_fill = uart_ra_fifo_fill,
|
|
.fifo_read = uart_ra_fifo_read,
|
|
.irq_tx_enable = uart_ra_irq_tx_enable,
|
|
.irq_tx_disable = uart_ra_irq_tx_disable,
|
|
.irq_tx_ready = uart_ra_irq_tx_ready,
|
|
.irq_rx_enable = uart_ra_irq_rx_enable,
|
|
.irq_rx_disable = uart_ra_irq_rx_disable,
|
|
.irq_rx_ready = uart_ra_irq_rx_ready,
|
|
.irq_err_enable = uart_ra_irq_err_enable,
|
|
.irq_err_disable = uart_ra_irq_err_disable,
|
|
.irq_is_pending = uart_ra_irq_is_pending,
|
|
.irq_update = uart_ra_irq_update,
|
|
.irq_callback_set = uart_ra_irq_callback_set,
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
};
|
|
|
|
/* Device Instantiation */
|
|
#define UART_RA_INIT_CFG(n) \
|
|
PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \
|
|
static const struct uart_ra_cfg uart_ra_cfg_##n = { \
|
|
.regs = DT_REG_ADDR(DT_INST_PARENT(n)), \
|
|
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
|
|
.clock_id = \
|
|
(clock_control_subsys_t)DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, id), \
|
|
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \
|
|
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \
|
|
.irq_config_func = irq_config_func_##n, \
|
|
)) \
|
|
}
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
|
|
#define RA_IRQ_CONNECT_DYNAMIC(n, name, dev, isr) \
|
|
ra_icu_irq_connect_dynamic(DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, irq), \
|
|
DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, priority), isr, dev, \
|
|
DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, flags));
|
|
|
|
#define RA_IRQ_DISCONNECT_DYNAMIC(n, name, dev, isr) \
|
|
ra_icu_irq_disconnect_dynamic(irqn, 0, NULL, NULL, 0)
|
|
|
|
#define UART_RA_CONFIG_FUNC(n) \
|
|
static int irq_config_func_##n(const struct device *dev) \
|
|
{ \
|
|
struct uart_ra_data *data = dev->data; \
|
|
int irqn; \
|
|
\
|
|
irqn = RA_IRQ_CONNECT_DYNAMIC(n, rxi, dev, uart_ra_isr_rxi); \
|
|
if (irqn < 0) { \
|
|
return irqn; \
|
|
} \
|
|
data->irqn[UART_RA_INT_RXI] = irqn; \
|
|
irqn = RA_IRQ_CONNECT_DYNAMIC(n, txi, dev, uart_ra_isr_txi); \
|
|
if (irqn < 0) { \
|
|
goto err_txi; \
|
|
} \
|
|
data->irqn[UART_RA_INT_TXI] = irqn; \
|
|
irqn = RA_IRQ_CONNECT_DYNAMIC(n, eri, dev, uart_ra_isr_eri); \
|
|
if (irqn < 0) { \
|
|
goto err_eri; \
|
|
} \
|
|
data->irqn[UART_RA_INT_ERI] = irqn; \
|
|
return 0; \
|
|
\
|
|
err_eri: \
|
|
RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_TXI], eri, dev, uart_ra_isr_eri); \
|
|
err_txi: \
|
|
RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_RXI], txi, dev, uart_ra_isr_txi); \
|
|
\
|
|
return irqn; \
|
|
}
|
|
#else
|
|
#define UART_RA_CONFIG_FUNC(n)
|
|
#endif
|
|
|
|
#define UART_RA_INIT(n) \
|
|
UART_RA_CONFIG_FUNC(n) \
|
|
UART_RA_INIT_CFG(n); \
|
|
\
|
|
static struct uart_ra_data uart_ra_data_##n = { \
|
|
.current_config = { \
|
|
.baudrate = DT_INST_PROP(n, current_speed), \
|
|
.parity = UART_CFG_PARITY_NONE, \
|
|
.stop_bits = UART_CFG_STOP_BITS_1, \
|
|
.data_bits = UART_CFG_DATA_BITS_8, \
|
|
.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
|
|
}, \
|
|
}; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(n, uart_ra_init, NULL, &uart_ra_data_##n, &uart_ra_cfg_##n, \
|
|
PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_ra_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(UART_RA_INIT)
|