08a2ca5b9b
According to the clic specification (https://github.com/riscv/riscv-fast-interrupt), the mnxti register has be written, in order to clear the pending bit for non-vectored interrupts. For vectored interrupts, this is automatically done. From the spec: "If the pending interrupt is edge-triggered, hardware will automatically clear the corresponding pending bit when the CSR instruction that accesses xnxti includes a write." I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented. For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that handles the pending interrupts according to the pseudo code in the spec. Signed-off-by: Greter Raffael <rgreter@baumer.com>
19 lines
598 B
Plaintext
19 lines
598 B
Plaintext
# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config NUCLEI_ECLIC
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bool "Enhanced Core Local Interrupt Controller (ECLIC)"
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default y
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depends on DT_HAS_NUCLEI_ECLIC_ENABLED
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select MULTI_LEVEL_INTERRUPTS
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select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE
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help
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Interrupt controller for Nuclei SoC core.
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config LEGACY_CLIC
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bool "Use the legacy clic specification"
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depends on RISCV_HAS_CLIC
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help
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Enables legacy clic, where smclicshv extension is not supported and
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hardware vectoring is set via mode bits of mtvec.
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