80a863f947
Add a stress test for sip_svc subsystem using INTEL SOCFPGA AGILEX platform. Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
10 lines
269 B
CMake
10 lines
269 B
CMake
# Copyright (c) 2023, Intel Corporation.
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(integration)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})
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