bc69500b0e
Add support for specifying the domain/kernel clock along with a common clock divider for the STM32H7 CAN controller driver via devicetree. Previously, the driver only supported using the PLL1_Q clock for domain/kernel clock, but now the driver defaults to the HSE clock, which is the chip default. Update existing boards to continue to use the PLL1_Q clock. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com> |
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| .. | ||
| doc | ||
| support | ||
| arduino_r3_connector.dtsi | ||
| board.cmake | ||
| Kconfig.board | ||
| Kconfig.defconfig | ||
| nucleo_h743zi.dts | ||
| nucleo_h743zi.yaml | ||
| nucleo_h743zi_defconfig | ||