Yong Cong Sin d1f3f863f1 soc/xtensa/intel_adsp: fix interrupts typo ... Hex should be `0x` instead of `0X` Signed-off-by: Yong Cong Sin <ycsin@meta.com>		2023-12-20 09:16:45 -05:00
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intel_adsp_ace15_mtpm.dtsi	dts: intel_adsp: ace remove dw watchdog	2023-11-10 16:22:34 -05:00
intel_adsp_ace20_lnl.dtsi	dts: adsp: ace20: remove lp clock	2023-09-18 10:35:23 +01:00
intel_adsp_cavs.dtsi	dts: xtensa: intel: add HDA DMA interrupt defs for cAVS platforms	2023-08-31 09:59:10 -04:00
intel_adsp_cavs15.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs18.dtsi	soc/xtensa/intel_adsp: fix interrupts typo	2023-12-20 09:16:45 -05:00
intel_adsp_cavs20.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs20_jsl.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs25.dtsi	soc: intel_adsp: cavs: fix dts memory address format	2023-11-06 15:40:20 -06:00
intel_adsp_cavs25_tgph.dtsi	soc: intel_adsp: cavs: fix dts memory address format	2023-11-06 15:40:20 -06:00