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zephyr/soc
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Carlo Caione 0e788b89a6 riscv: Use IRQ vector table for vectored mode 
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 10:00:20 +02:00
..
arc soc: add mising braces to single line if statements 2022-07-06 11:00:45 -04:00
arm soc: add mising braces to single line if statements 2022-07-06 11:00:45 -04:00
arm64 xenvm: drivers: xen: add Xen grant table driver 2022-06-28 22:34:26 -04:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
riscv riscv: Use IRQ vector table for vectored mode 2022-07-07 10:00:20 +02:00
sparc linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 uart_pipe: Remove obsolete UART_PIPE_ON_DEV_NAME Kconfig 2022-07-07 09:59:49 +02:00
xtensa intel: adsp: Simplify PM 2022-07-07 02:10:11 -04:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00