174824f1cb
1. Move the GPIO mux setting to the soc layer. The GPIO MUX value may vary based on the SoC Family 2. Enable the digital input buffer if available Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
347 lines
9 KiB
C
347 lines
9 KiB
C
/*
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* Copyright (c) 2016 Freescale Semiconductor, Inc.
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_kinetis_gpio
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/dt-bindings/gpio/nxp-kinetis-gpio.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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struct gpio_mcux_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *gpio_base;
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PORT_Type *port_base;
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unsigned int flags;
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};
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struct gpio_mcux_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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static int gpio_mcux_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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PORT_Type *port_base = config->port_base;
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uint32_t mask = 0U;
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uint32_t pcr = 0U;
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/* Check for an invalid pin number */
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if (pin >= ARRAY_SIZE(port_base->PCR)) {
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return -EINVAL;
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}
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/* The flags contain options that require touching registers in the
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* GPIO module and the corresponding PORT module.
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*
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* Start with the GPIO module and set up the pin direction register.
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* 0 - pin is input, 1 - pin is output
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*/
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switch (flags & GPIO_DIR_MASK) {
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case GPIO_INPUT:
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gpio_base->PDDR &= ~BIT(pin);
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break;
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case GPIO_OUTPUT:
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_base->PSOR = BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_base->PCOR = BIT(pin);
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}
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gpio_base->PDDR |= BIT(pin);
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break;
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default:
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return -ENOTSUP;
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}
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/* Set PCR mux to GPIO for the pin we are configuring */
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mask |= PORT_PCR_MUX_MASK;
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pcr |= PORT_PCR_MUX(PORT_MUX_GPIO);
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#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
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/* Enable digital input buffer */
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pcr |= PORT_PCR_IBE_MASK;
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#endif
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/* Now do the PORT module. Figure out the pullup/pulldown
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* configuration, but don't write it to the PCR register yet.
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*/
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mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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if ((flags & GPIO_PULL_UP) != 0) {
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/* Enable the pull and select the pullup resistor. */
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pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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/* Enable the pull and select the pulldown resistor (deselect
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* the pullup resistor.
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*/
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pcr |= PORT_PCR_PE_MASK;
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}
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#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
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/* Determine the drive strength */
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switch (flags & KINETIS_GPIO_DS_MASK) {
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case KINETIS_GPIO_DS_DFLT:
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/* Default is low drive strength */
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mask |= PORT_PCR_DSE_MASK;
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break;
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case KINETIS_GPIO_DS_ALT:
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/* Alternate is high drive strength */
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pcr |= PORT_PCR_DSE_MASK;
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break;
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default:
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return -ENOTSUP;
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}
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#endif /* defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
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/* Accessing by pin, we only need to write one PCR register. */
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port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
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return 0;
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}
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static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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*value = gpio_base->PDIR;
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return 0;
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}
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static int gpio_mcux_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_mcux_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PSOR = mask;
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return 0;
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}
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static int gpio_mcux_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PCOR = mask;
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return 0;
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}
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static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PTOR = mask;
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return 0;
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}
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static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
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uint32_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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port_interrupt_t port_interrupt = 0;
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if (mode == GPIO_INT_MODE_DISABLED) {
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port_interrupt = kPORT_InterruptOrDMADisabled;
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} else {
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if (mode == GPIO_INT_MODE_LEVEL) {
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if (trig == GPIO_INT_TRIG_LOW) {
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port_interrupt = kPORT_InterruptLogicZero;
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} else {
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port_interrupt = kPORT_InterruptLogicOne;
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}
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} else {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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port_interrupt = kPORT_InterruptFallingEdge;
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break;
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case GPIO_INT_TRIG_HIGH:
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port_interrupt = kPORT_InterruptRisingEdge;
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break;
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case GPIO_INT_TRIG_BOTH:
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port_interrupt = kPORT_InterruptEitherEdge;
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break;
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}
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}
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}
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return PORT_PCR_IRQC(port_interrupt);
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}
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static int gpio_mcux_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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PORT_Type *port_base = config->port_base;
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/* Check for an invalid pin number */
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if (pin >= ARRAY_SIZE(port_base->PCR)) {
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return -EINVAL;
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}
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/* Check for an invalid pin configuration */
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if ((mode != GPIO_INT_MODE_DISABLED) &&
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((gpio_base->PDDR & BIT(pin)) != 0)) {
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return -EINVAL;
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}
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/* Check if GPIO port supports interrupts */
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if ((mode != GPIO_INT_MODE_DISABLED) &&
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((config->flags & GPIO_INT_ENABLE) == 0U)) {
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return -ENOTSUP;
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}
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uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
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port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
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return 0;
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}
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static int gpio_mcux_manage_callback(const struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_mcux_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static void gpio_mcux_port_isr(const struct device *dev)
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{
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const struct gpio_mcux_config *config = dev->config;
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struct gpio_mcux_data *data = dev->data;
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uint32_t int_status;
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int_status = config->port_base->ISFR;
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/* Clear the port interrupts */
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config->port_base->ISFR = int_status;
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gpio_fire_callbacks(&data->callbacks, dev, int_status);
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}
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#ifdef CONFIG_GPIO_GET_DIRECTION
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static int gpio_mcux_port_get_direction(const struct device *dev, gpio_port_pins_t map,
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gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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map &= config->common.port_pin_mask;
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if (inputs != NULL) {
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*inputs = map & (~gpio_base->PDDR);
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}
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if (outputs != NULL) {
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*outputs = map & gpio_base->PDDR;
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}
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return 0;
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}
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#endif /* CONFIG_GPIO_GET_DIRECTION */
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static const struct gpio_driver_api gpio_mcux_driver_api = {
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.pin_configure = gpio_mcux_configure,
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.port_get_raw = gpio_mcux_port_get_raw,
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.port_set_masked_raw = gpio_mcux_port_set_masked_raw,
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.port_set_bits_raw = gpio_mcux_port_set_bits_raw,
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.port_clear_bits_raw = gpio_mcux_port_clear_bits_raw,
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.port_toggle_bits = gpio_mcux_port_toggle_bits,
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.pin_interrupt_configure = gpio_mcux_pin_interrupt_configure,
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.manage_callback = gpio_mcux_manage_callback,
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#ifdef CONFIG_GPIO_GET_DIRECTION
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.port_get_direction = gpio_mcux_port_get_direction,
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#endif /* CONFIG_GPIO_GET_DIRECTION */
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};
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#define GPIO_MCUX_IRQ_INIT(n) \
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do { \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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gpio_mcux_port_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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} while (false)
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#define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port))
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#define GPIO_DEVICE_INIT_MCUX(n) \
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static int gpio_mcux_port## n ## _init(const struct device *dev); \
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\
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static const struct gpio_mcux_config gpio_mcux_port## n ## _config = {\
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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.gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n), \
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.port_base = (PORT_Type *) GPIO_PORT_BASE_ADDR(n), \
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.flags = UTIL_AND(DT_INST_IRQ_HAS_IDX(n, 0), GPIO_INT_ENABLE),\
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}; \
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\
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static struct gpio_mcux_data gpio_mcux_port## n ##_data; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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gpio_mcux_port## n ##_init, \
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NULL, \
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&gpio_mcux_port## n ##_data, \
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&gpio_mcux_port## n##_config, \
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POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_mcux_driver_api); \
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\
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static int gpio_mcux_port## n ##_init(const struct device *dev) \
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{ \
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
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(GPIO_MCUX_IRQ_INIT(n);)) \
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return 0; \
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}
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DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT_MCUX)
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