9fab38dd04
Modify the NPCX driver erase method to allow 0x1000 byte size erases along with 0x10000 byte size erases based on input parameters Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
50 lines
1.6 KiB
YAML
50 lines
1.6 KiB
YAML
# Copyright (c) 2023 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The SPI NOR flash devices accessed by Nuvoton Flash Interface Unit (FIU).
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Representation of a SPI NOR flash on a qspi bus looks like:
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int_flash: w25q40@0 {
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compatible ="nuvoton,npcx-fiu-nor";
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size = <DT_SIZE_K(512 * 8)>;
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reg = <0>;
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qspi-flags = <NPCX_QSPI_SW_CS1>;
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mapped-addr = <0x64000000>;
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pinctrl-0 = <&int_flash_sl>;
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pinctrl-names = "default";
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};
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compatible: "nuvoton,npcx-fiu-nor"
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include: [flash-controller.yaml, pinctrl-device.yaml, "jedec,spi-nor-common.yaml"]
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on-bus: qspi
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properties:
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mapped-addr:
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type: int
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required: true
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description: Mapped memory address of direct read access for spi nor flash.
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max-timeout:
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type: int
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default: 10000
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description: Typically, it equals to max timeout of chip erase in ms.
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qspi-flags:
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type: int
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required: true
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description: The definitions for configuring the Quad-SPI peripherals.
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rd-mode:
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type: string
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default: "NPCX_RD_MODE_FAST_DUAL"
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description: |
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Selects the SPI read access type of Direct Read Access. Usually, we choose
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Fast Read Dual I/O mode for better performance. If the nor spi flash does
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not support this mode, please set this property explicitly.
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enum:
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- "NPCX_RD_MODE_NORMAL" # Direct read access by command code 03h
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- "NPCX_RD_MODE_FAST" # Direct read access by command code 0bh
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- "NPCX_RD_MODE_FAST_DUAL" # Direct read access by command code bbh
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