12665a0dc1
This patch set provides support for T1S ethernet device - LAN8651. For SPI communication the implementation of Open Alliance TC6 specification is used. The driver implementation focuses mostly on reducing memory footprint, as the used SoC (STM32G491) for development has only 32 KiB RAM in total. Signed-off-by: Lukasz Majewski <lukma@denx.de>
586 lines
17 KiB
C
586 lines
17 KiB
C
/*
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* Copyright (c) 2023 DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_lan865x
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(eth_lan865x, CONFIG_ETHERNET_LOG_LEVEL);
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#include <zephyr/net/ethernet.h>
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#include <zephyr/net/phy.h>
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#include <string.h>
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#include <errno.h>
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#include <zephyr/net/net_if.h>
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#include <zephyr/net/ethernet.h>
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#include <zephyr/net/phy.h>
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#include "eth_lan865x_priv.h"
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static int lan865x_mac_rxtx_control(const struct device *dev, bool en)
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{
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struct lan865x_data *ctx = dev->data;
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uint32_t ctl = 0;
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if (en) {
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ctl = LAN865x_MAC_NCR_TXEN | LAN865x_MAC_NCR_RXEN;
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}
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return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCR, ctl);
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}
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static void lan865x_iface_init(struct net_if *iface)
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{
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const struct device *dev = net_if_get_device(iface);
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struct lan865x_data *ctx = dev->data;
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net_if_set_link_addr(iface, ctx->mac_address, sizeof(ctx->mac_address),
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NET_LINK_ETHERNET);
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if (ctx->iface == NULL) {
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ctx->iface = iface;
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}
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ethernet_init(iface);
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net_eth_carrier_on(iface);
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ctx->iface_initialized = true;
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}
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static enum ethernet_hw_caps lan865x_port_get_capabilities(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return ETHERNET_LINK_10BASE_T | ETHERNET_PROMISC_MODE;
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}
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static void lan865x_write_macaddress(const struct device *dev);
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static int lan865x_set_config(const struct device *dev, enum ethernet_config_type type,
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const struct ethernet_config *config)
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{
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struct lan865x_data *ctx = dev->data;
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int ret = -ENOTSUP;
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if (type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
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ret = lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_OFF);
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if (ret) {
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return ret;
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}
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ret = oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCFGR,
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LAN865x_MAC_NCFGR_CAF);
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if (ret) {
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return ret;
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}
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return lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_ON);
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}
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if (type == ETHERNET_CONFIG_TYPE_MAC_ADDRESS) {
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ret = lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_OFF);
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if (ret) {
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return ret;
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}
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memcpy(ctx->mac_address, config->mac_address.addr,
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sizeof(ctx->mac_address));
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lan865x_write_macaddress(dev);
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net_if_set_link_addr(ctx->iface, ctx->mac_address,
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sizeof(ctx->mac_address),
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NET_LINK_ETHERNET);
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return lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_ON);
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}
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return ret;
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}
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static int lan865x_wait_for_reset(const struct device *dev)
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{
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struct lan865x_data *ctx = dev->data;
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uint8_t i;
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/* Wait for end of LAN865x reset */
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for (i = 0; !ctx->reset && i < LAN865X_RESET_TIMEOUT; i++) {
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k_msleep(1);
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}
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if (i == LAN865X_RESET_TIMEOUT) {
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LOG_ERR("LAN865x reset timeout reached!");
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return -ENODEV;
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}
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return 0;
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}
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static int lan865x_gpio_reset(const struct device *dev)
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{
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const struct lan865x_config *cfg = dev->config;
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/* Perform (GPIO based) HW reset */
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/* assert RESET_N low for 10 µs (5 µs min) */
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gpio_pin_set_dt(&cfg->reset, 1);
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k_busy_wait(10U);
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/* deassert - end of reset indicated by IRQ_N low */
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gpio_pin_set_dt(&cfg->reset, 0);
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return lan865x_wait_for_reset(dev);
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}
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static int lan865x_check_spi(const struct device *dev)
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{
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struct lan865x_data *ctx = dev->data;
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uint32_t val;
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int ret;
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ret = oa_tc6_reg_read(ctx->tc6, LAN865x_DEVID, &val);
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if (ret < 0) {
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return -ENODEV;
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}
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ctx->silicon_rev = val & LAN865X_REV_MASK;
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if (ctx->silicon_rev != 1 && ctx->silicon_rev != 2) {
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return -ENODEV;
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}
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ctx->chip_id = (val >> 4) & 0xFFFF;
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if (ctx->chip_id != LAN8650_DEVID && ctx->chip_id != LAN8651_DEVID) {
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return -ENODEV;
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}
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return ret;
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}
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/* Implementation of pseudo code from AN1760 */
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static uint8_t lan865x_read_indirect_reg(const struct device *dev, uint8_t addr,
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uint8_t mask)
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{
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struct lan865x_data *ctx = dev->data;
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uint32_t val;
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oa_tc6_reg_write(ctx->tc6, 0x000400D8, addr);
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oa_tc6_reg_write(ctx->tc6, 0x000400DA, 0x02);
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oa_tc6_reg_read(ctx->tc6, 0x000400D9, &val);
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return (uint8_t) val & mask;
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}
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static int lan865x_init_chip(const struct device *dev, uint8_t silicon_rev)
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{
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struct lan865x_data *ctx = dev->data;
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uint8_t value1, value2;
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int8_t offset1 = 0, offset2 = 0, ret;
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uint16_t value3, value4, value5, value6, value7;
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uint16_t cfgparam1, cfgparam2, cfgparam3, cfgparam4, cfgparam5;
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uint32_t val;
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ret = lan865x_read_indirect_reg(dev, 0x05, 0x40);
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if (ret == 0) {
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LOG_ERR("LAN865x error! Please contact microchip support for replacement.");
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return -EIO;
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}
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value1 = lan865x_read_indirect_reg(dev, 0x04, 0x1F);
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if ((value1 & 0x10) != 0) { /* Convert uint8_t to int8_t */
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offset1 = value1 | 0xE0;
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if (offset1 < -5) {
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LOG_ERR("LAN865x internal error!");
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return -EIO;
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}
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} else {
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offset1 = value1;
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}
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value2 = lan865x_read_indirect_reg(dev, 0x08, 0x1F);
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if ((value2 & 0x10) != 0) { /* Convert uint8_t to int8_t */
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offset2 = value2 | 0xE0;
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} else {
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offset2 = value2;
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}
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oa_tc6_reg_read(ctx->tc6, 0x00040084, &val);
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value3 = (uint16_t)val;
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oa_tc6_reg_read(ctx->tc6, 0x0004008A, &val);
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value4 = (uint16_t)val;
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oa_tc6_reg_read(ctx->tc6, 0x000400AD, &val);
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value5 = (uint16_t)val;
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oa_tc6_reg_read(ctx->tc6, 0x000400AE, &val);
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value6 = (uint8_t)val;
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oa_tc6_reg_read(ctx->tc6, 0x000400AF, &val);
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value7 = (uint8_t)val;
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cfgparam1 = (value3 & 0xF) | (((9 + offset1) << 10) | ((14 + offset1) << 4));
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cfgparam2 = (value4 & 0x3FF) | ((40 + offset2) << 10);
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cfgparam3 = (value5 & 0xC0C0) | (((5 + offset1) << 8) | (9 + offset1));
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cfgparam4 = (value6 & 0xC0C0) | (((9 + offset1) << 8) | (14 + offset1));
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cfgparam5 = (value7 & 0xC0C0) | (((17 + offset1) << 8) | (22 + offset1));
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oa_tc6_reg_write(ctx->tc6, 0x00040084, (uint32_t) cfgparam1);
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oa_tc6_reg_write(ctx->tc6, 0x0004008A, (uint32_t) cfgparam2);
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oa_tc6_reg_write(ctx->tc6, 0x000400AD, (uint32_t) cfgparam3);
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oa_tc6_reg_write(ctx->tc6, 0x000400AE, (uint32_t) cfgparam4);
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oa_tc6_reg_write(ctx->tc6, 0x000400AF, (uint32_t) cfgparam5);
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return 0;
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}
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/* Implementation of pseudo code from AN1760 - END */
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static int lan865x_config_plca(const struct device *dev, uint8_t node_id,
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uint8_t node_cnt, uint8_t burst_cnt, uint8_t burst_timer)
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{
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struct lan865x_data *ctx = dev->data;
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uint32_t val;
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/* Collision Detection */
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oa_tc6_reg_write(ctx->tc6, 0x00040087, 0x0083u); /* COL_DET_CTRL0 */
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/* T1S Phy Node Id and Max Node Count */
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val = ((uint32_t)node_cnt << 8) | node_id;
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oa_tc6_reg_write(ctx->tc6, 0x0004CA02, val); /* PLCA_CONTROL_1_REGISTER */
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/* PLCA Burst Count and Burst Timer */
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val = ((uint32_t)burst_cnt << 8) | burst_timer;
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oa_tc6_reg_write(ctx->tc6, 0x0004CA05, val); /* PLCA_BURST_MODE_REGISTER */
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/* Enable PLCA */
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oa_tc6_reg_write(ctx->tc6, 0x0004CA01, BIT(15)); /* PLCA_CONTROL_0_REGISTER */
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return 0;
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}
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static void lan865x_write_macaddress(const struct device *dev)
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{
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struct lan865x_data *ctx = dev->data;
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uint8_t *mac = &ctx->mac_address[0];
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uint32_t val;
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/* SPEC_ADD2_BOTTOM */
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val = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
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oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_SAB2, val);
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/* SPEC_ADD2_TOP */
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val = (mac[5] << 8) | mac[4];
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oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_SAT2, val);
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/* SPEC_ADD1_BOTTOM */
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val = (mac[5] << 24) | (mac[4] << 16) | (mac[3] << 8) | mac[2];
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oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_SAB1, val);
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}
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static int lan865x_default_config(const struct device *dev, uint8_t silicon_rev)
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{
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/* Values in the below table are the same for LAN865x rev. B0 and B1 */
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static const oa_mem_map_t lan865x_conf[] = {
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{ .address = 0x00010000, .value = 0x00000000 },
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{ .address = 0x00040091, .value = 0x00009660 },
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{ .address = 0x00040081, .value = 0x00000080 },
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{ .address = 0x00010077, .value = 0x00000028 },
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{ .address = 0x00040043, .value = 0x000000FF },
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{ .address = 0x00040044, .value = 0x0000FFFF },
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{ .address = 0x00040045, .value = 0x00000000 },
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{ .address = 0x00040053, .value = 0x000000FF },
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{ .address = 0x00040054, .value = 0x0000FFFF },
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{ .address = 0x00040055, .value = 0x00000000 },
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{ .address = 0x00040040, .value = 0x00000002 },
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{ .address = 0x00040050, .value = 0x00000002 },
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{ .address = 0x000400E9, .value = 0x00009E50 },
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{ .address = 0x000400F5, .value = 0x00001CF8 },
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{ .address = 0x000400F4, .value = 0x0000C020 },
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{ .address = 0x000400F8, .value = 0x00009B00 },
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{ .address = 0x000400F9, .value = 0x00004E53 },
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{ .address = 0x000400B0, .value = 0x00000103 },
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{ .address = 0x000400B1, .value = 0x00000910 },
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{ .address = 0x000400B2, .value = 0x00001D26 },
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{ .address = 0x000400B3, .value = 0x0000002A },
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{ .address = 0x000400B4, .value = 0x00000103 },
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{ .address = 0x000400B5, .value = 0x0000070D },
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{ .address = 0x000400B6, .value = 0x00001720 },
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{ .address = 0x000400B7, .value = 0x00000027 },
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{ .address = 0x000400B8, .value = 0x00000509 },
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{ .address = 0x000400B9, .value = 0x00000E13 },
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{ .address = 0x000400BA, .value = 0x00001C25 },
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{ .address = 0x000400BB, .value = 0x0000002B },
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{ .address = 0x0000000C, .value = 0x00000100 },
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{ .address = 0x00040081, .value = 0x000000E0 },
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};
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const struct lan865x_config *cfg = dev->config;
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uint8_t i, size = ARRAY_SIZE(lan865x_conf);
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struct lan865x_data *ctx = dev->data;
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int ret;
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/* Enable protected control RW */
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oa_tc6_set_protected_ctrl(ctx->tc6, true);
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for (i = 0; i < size; i++) {
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oa_tc6_reg_write(ctx->tc6, lan865x_conf[i].address,
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lan865x_conf[i].value);
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}
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if (silicon_rev == 1) {
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/* For silicon rev 1 (B0): (bit [3..0] from 0x0A0084 */
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oa_tc6_reg_write(ctx->tc6, 0x000400D0, 0x5F21);
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}
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lan865x_write_macaddress(dev);
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ret = lan865x_init_chip(dev, silicon_rev);
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if (ret < 0)
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return ret;
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if (cfg->plca_enable) {
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ret = lan865x_config_plca(dev, cfg->plca_node_id,
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cfg->plca_node_count,
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cfg->plca_burst_count,
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cfg->plca_burst_timer);
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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static void lan865x_int_callback(const struct device *dev,
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struct gpio_callback *cb,
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uint32_t pins)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(pins);
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struct lan865x_data *ctx =
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CONTAINER_OF(cb, struct lan865x_data, gpio_int_callback);
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k_sem_give(&ctx->int_sem);
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}
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static void lan865x_read_chunks(const struct device *dev)
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{
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const struct lan865x_config *cfg = dev->config;
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struct lan865x_data *ctx = dev->data;
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struct oa_tc6 *tc6 = ctx->tc6;
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struct net_pkt *pkt;
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int ret;
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k_sem_take(&ctx->tx_rx_sem, K_FOREVER);
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pkt = net_pkt_rx_alloc(K_MSEC(cfg->timeout));
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if (!pkt) {
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LOG_ERR("OA RX: Could not allocate packet!");
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k_sem_give(&ctx->tx_rx_sem);
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return;
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}
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ret = oa_tc6_read_chunks(tc6, pkt);
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k_sem_give(&ctx->tx_rx_sem);
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if (ret < 0) {
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eth_stats_update_errors_rx(ctx->iface);
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net_pkt_unref(pkt);
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return;
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}
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/* Feed buffer frame to IP stack */
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ret = net_recv_data(ctx->iface, pkt);
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if (ret < 0) {
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LOG_ERR("OA RX: Could not process packet (%d)!", ret);
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net_pkt_unref(pkt);
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}
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}
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static void lan865x_int_thread(const struct device *dev)
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{
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struct lan865x_data *ctx = dev->data;
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struct oa_tc6 *tc6 = ctx->tc6;
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uint32_t sts, val, ftr;
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while (true) {
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k_sem_take(&ctx->int_sem, K_FOREVER);
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if (!ctx->reset) {
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oa_tc6_reg_read(tc6, OA_STATUS0, &sts);
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if (sts & OA_STATUS0_RESETC) {
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oa_tc6_reg_write(tc6, OA_STATUS0, sts);
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lan865x_default_config(dev, ctx->silicon_rev);
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oa_tc6_reg_read(tc6, OA_CONFIG0, &val);
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oa_tc6_reg_write(tc6, OA_CONFIG0, OA_CONFIG0_SYNC | val);
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lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_ON);
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ctx->reset = true;
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/*
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* According to OA T1S standard - it is mandatory to
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* read chunk of data to get the IRQ_N negated (deasserted).
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*/
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oa_tc6_read_status(tc6, &ftr);
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continue;
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}
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}
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/*
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* The IRQ_N is asserted when RCA becomes > 0, so update its value
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* before reading chunks.
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*/
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oa_tc6_update_buf_info(tc6);
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while (tc6->rca > 0) {
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lan865x_read_chunks(dev);
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}
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if (tc6->exst) {
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/*
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* Just clear any pending interrupts - data RX will be served
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* earlier.
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* The RESETC is handled separately as it requires LAN865x device
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* configuration.
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*/
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oa_tc6_reg_read(tc6, OA_STATUS0, &sts);
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if (sts != 0) {
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oa_tc6_reg_write(tc6, OA_STATUS0, sts);
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}
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oa_tc6_reg_read(tc6, OA_STATUS1, &sts);
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if (sts != 0) {
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oa_tc6_reg_write(tc6, OA_STATUS1, sts);
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}
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}
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}
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}
|
|
|
|
static int lan865x_init(const struct device *dev)
|
|
{
|
|
const struct lan865x_config *cfg = dev->config;
|
|
struct lan865x_data *ctx = dev->data;
|
|
int ret;
|
|
|
|
__ASSERT(cfg->spi.config.frequency <= LAN865X_SPI_MAX_FREQUENCY,
|
|
"SPI frequency exceeds supported maximum\n");
|
|
|
|
if (!spi_is_ready_dt(&cfg->spi)) {
|
|
LOG_ERR("SPI bus %s not ready", cfg->spi.bus->name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!gpio_is_ready_dt(&cfg->interrupt)) {
|
|
LOG_ERR("Interrupt GPIO device %s is not ready",
|
|
cfg->interrupt.port->name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Check SPI communication after reset */
|
|
ret = lan865x_check_spi(dev);
|
|
if (ret < 0) {
|
|
LOG_ERR("SPI communication not working, %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Configure interrupt service routine for LAN865x IRQ
|
|
*/
|
|
ret = gpio_pin_configure_dt(&cfg->interrupt, GPIO_INPUT);
|
|
if (ret < 0) {
|
|
LOG_ERR("Failed to configure interrupt GPIO, %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
gpio_init_callback(&(ctx->gpio_int_callback), lan865x_int_callback,
|
|
BIT(cfg->interrupt.pin));
|
|
|
|
ret = gpio_add_callback(cfg->interrupt.port, &ctx->gpio_int_callback);
|
|
if (ret < 0) {
|
|
LOG_ERR("Failed to add INT callback, %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
|
|
|
|
/* Start interruption-poll thread */
|
|
ctx->tid_int =
|
|
k_thread_create(&ctx->thread, ctx->thread_stack,
|
|
CONFIG_ETH_LAN865X_IRQ_THREAD_STACK_SIZE,
|
|
(k_thread_entry_t)lan865x_int_thread,
|
|
(void *)dev, NULL, NULL,
|
|
K_PRIO_COOP(CONFIG_ETH_LAN865X_IRQ_THREAD_PRIO),
|
|
0, K_NO_WAIT);
|
|
k_thread_name_set(ctx->tid_int, "lan865x_interrupt");
|
|
|
|
ctx->reset = false;
|
|
|
|
/* Perform HW reset - 'rst-gpios' required property set in DT */
|
|
if (!gpio_is_ready_dt(&cfg->reset)) {
|
|
LOG_ERR("Reset GPIO device %s is not ready",
|
|
cfg->reset.port->name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_INACTIVE);
|
|
if (ret < 0) {
|
|
LOG_ERR("Failed to configure reset GPIO, %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
return lan865x_gpio_reset(dev);
|
|
}
|
|
|
|
static int lan865x_port_send(const struct device *dev, struct net_pkt *pkt)
|
|
{
|
|
struct lan865x_data *ctx = dev->data;
|
|
struct oa_tc6 *tc6 = ctx->tc6;
|
|
int ret;
|
|
|
|
k_sem_take(&ctx->tx_rx_sem, K_FOREVER);
|
|
ret = oa_tc6_send_chunks(tc6, pkt);
|
|
k_sem_give(&ctx->tx_rx_sem);
|
|
if (ret < 0) {
|
|
LOG_ERR("TX transmission error, %d", ret);
|
|
eth_stats_update_errors_tx(net_pkt_iface(pkt));
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ethernet_api lan865x_api_func = {
|
|
.iface_api.init = lan865x_iface_init,
|
|
.get_capabilities = lan865x_port_get_capabilities,
|
|
.set_config = lan865x_set_config,
|
|
.send = lan865x_port_send,
|
|
};
|
|
|
|
#define LAN865X_DEFINE(inst) \
|
|
static const struct lan865x_config lan865x_config_##inst = { \
|
|
.spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0), \
|
|
.interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \
|
|
.reset = GPIO_DT_SPEC_INST_GET(inst, rst_gpios), \
|
|
.timeout = CONFIG_ETH_LAN865X_TIMEOUT, \
|
|
.plca_node_id = DT_INST_PROP(inst, plca_node_id), \
|
|
.plca_node_count = DT_INST_PROP(inst, plca_node_count), \
|
|
.plca_burst_count = DT_INST_PROP(inst, plca_burst_count), \
|
|
.plca_burst_timer = DT_INST_PROP(inst, plca_burst_timer), \
|
|
.plca_to_timer = DT_INST_PROP(inst, plca_to_timer), \
|
|
.plca_enable = DT_INST_PROP(inst, plca_enable), \
|
|
}; \
|
|
\
|
|
struct oa_tc6 oa_tc6_##inst = { \
|
|
.cps = 64, \
|
|
.protected = 0, \
|
|
.spi = &lan865x_config_##inst.spi \
|
|
}; \
|
|
static struct lan865x_data lan865x_data_##inst = { \
|
|
.mac_address = DT_INST_PROP(inst, local_mac_address), \
|
|
.tx_rx_sem = \
|
|
Z_SEM_INITIALIZER((lan865x_data_##inst).tx_rx_sem, 1, UINT_MAX), \
|
|
.int_sem = Z_SEM_INITIALIZER((lan865x_data_##inst).int_sem, 0, UINT_MAX), \
|
|
.tc6 = &oa_tc6_##inst \
|
|
}; \
|
|
\
|
|
ETH_NET_DEVICE_DT_INST_DEFINE(inst, lan865x_init, NULL, &lan865x_data_##inst, \
|
|
&lan865x_config_##inst, CONFIG_ETH_INIT_PRIORITY, \
|
|
&lan865x_api_func, NET_ETH_MTU);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(LAN865X_DEFINE);
|