88ca215eed
Updates the API and types to match updated I2C terminology. Replaces master with controller and slave with target. Updates all drivers to match the changed macros, types, and API signatures. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
343 lines
7.4 KiB
C
343 lines
7.4 KiB
C
/*
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* Copyright (c) 2018 SiFive Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifive_i2c0
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(i2c_sifive);
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#include <zephyr/device.h>
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#include <zephyr/drivers/i2c.h>
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#include <soc.h>
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#include <zephyr/sys/sys_io.h>
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#include "i2c-priv.h"
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/* Macros */
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#define I2C_REG(config, reg) ((mem_addr_t) ((config)->base + reg))
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#define IS_SET(config, reg, value) (sys_read8(I2C_REG(config, reg)) & (value))
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/* Register Offsets */
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#define REG_PRESCALE_LOW 0x00
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#define REG_PRESCALE_HIGH 0x04
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#define REG_CONTROL 0x08
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/* Transmit on write, receive on read */
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#define REG_TRANSMIT 0x0c
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#define REG_RECEIVE 0x0c
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/* Command on write, status on read */
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#define REG_COMMAND 0x10
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#define REG_STATUS 0x10
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/* Values */
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#define SF_CONTROL_EN (1 << 7)
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#define SF_CONTROL_IE (1 << 6)
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#define SF_TX_WRITE (0 << 0)
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#define SF_TX_READ (1 << 0)
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#define SF_CMD_START (1 << 7)
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#define SF_CMD_STOP (1 << 6)
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#define SF_CMD_READ (1 << 5)
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#define SF_CMD_WRITE (1 << 4)
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#define SF_CMD_ACK (1 << 3)
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#define SF_CMD_IACK (1 << 0)
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#define SF_STATUS_RXACK (1 << 7)
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#define SF_STATUS_BUSY (1 << 6)
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#define SF_STATUS_AL (1 << 5)
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#define SF_STATUS_TIP (1 << 1)
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#define SF_STATUS_IP (1 << 0)
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/* Structure declarations */
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struct i2c_sifive_cfg {
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uint32_t base;
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uint32_t f_sys;
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uint32_t f_bus;
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};
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/* Helper functions */
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static inline bool i2c_sifive_busy(const struct device *dev)
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{
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const struct i2c_sifive_cfg *config = dev->config;
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return IS_SET(config, REG_STATUS, SF_STATUS_TIP);
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}
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static int i2c_sifive_send_addr(const struct device *dev,
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uint16_t addr,
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uint16_t rw_flag)
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{
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const struct i2c_sifive_cfg *config = dev->config;
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uint8_t command = 0U;
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/* Wait for a previous transfer to complete */
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while (i2c_sifive_busy(dev)) {
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}
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/* Set transmit register to address with read/write flag */
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sys_write8((addr | rw_flag), I2C_REG(config, REG_TRANSMIT));
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/* Addresses are always written */
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command = SF_CMD_WRITE | SF_CMD_START;
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/* Write the command register to start the transfer */
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sys_write8(command, I2C_REG(config, REG_COMMAND));
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while (i2c_sifive_busy(dev)) {
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}
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if (IS_SET(config, REG_STATUS, SF_STATUS_RXACK)) {
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LOG_ERR("I2C Rx failed to acknowledge\n");
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return -EIO;
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}
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return 0;
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}
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static int i2c_sifive_write_msg(const struct device *dev,
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struct i2c_msg *msg,
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uint16_t addr)
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{
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const struct i2c_sifive_cfg *config = dev->config;
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int rc = 0;
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uint8_t command = 0U;
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rc = i2c_sifive_send_addr(dev, addr, SF_TX_WRITE);
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if (rc != 0) {
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LOG_ERR("I2C failed to write message\n");
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return rc;
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}
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for (uint32_t i = 0; i < msg->len; i++) {
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/* Wait for a previous transfer */
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while (i2c_sifive_busy(dev)) {
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}
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/* Put data in transmit reg */
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sys_write8((msg->buf)[i], I2C_REG(config, REG_TRANSMIT));
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/* Generate command byte */
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command = SF_CMD_WRITE;
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/* On the last byte of the message */
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if (i == (msg->len - 1)) {
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/* If the stop bit is requested, set it */
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if (msg->flags & I2C_MSG_STOP) {
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command |= SF_CMD_STOP;
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}
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}
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/* Write command reg */
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sys_write8(command, I2C_REG(config, REG_COMMAND));
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/* Wait for a previous transfer */
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while (i2c_sifive_busy(dev)) {
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}
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if (IS_SET(config, REG_STATUS, SF_STATUS_RXACK)) {
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LOG_ERR("I2C Rx failed to acknowledge\n");
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return -EIO;
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}
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}
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return 0;
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}
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static int i2c_sifive_read_msg(const struct device *dev,
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struct i2c_msg *msg,
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uint16_t addr)
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{
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const struct i2c_sifive_cfg *config = dev->config;
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uint8_t command = 0U;
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i2c_sifive_send_addr(dev, addr, SF_TX_READ);
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while (i2c_sifive_busy(dev)) {
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}
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for (int i = 0; i < msg->len; i++) {
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/* Generate command byte */
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command = SF_CMD_READ;
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/* On the last byte of the message */
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if (i == (msg->len - 1)) {
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/* Set NACK to end read */
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command |= SF_CMD_ACK;
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/* If the stop bit is requested, set it */
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if (msg->flags & I2C_MSG_STOP) {
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command |= SF_CMD_STOP;
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}
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}
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/* Write command reg */
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sys_write8(command, I2C_REG(config, REG_COMMAND));
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/* Wait for the read to complete */
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while (i2c_sifive_busy(dev)) {
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}
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/* Store the received byte */
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(msg->buf)[i] = sys_read8(I2C_REG(config, REG_RECEIVE));
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}
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return 0;
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}
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/* API Functions */
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static int i2c_sifive_configure(const struct device *dev, uint32_t dev_config)
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{
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const struct i2c_sifive_cfg *config = NULL;
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uint32_t i2c_speed = 0U;
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uint16_t prescale = 0U;
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/* Check for NULL pointers */
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if (dev == NULL) {
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LOG_ERR("Device handle is NULL");
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return -EINVAL;
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}
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config = dev->config;
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if (config == NULL) {
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LOG_ERR("Device config is NULL");
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return -EINVAL;
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}
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/* Disable the I2C peripheral */
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sys_write8(0, I2C_REG(config, REG_CONTROL));
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/* Configure bus frequency */
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switch (I2C_SPEED_GET(dev_config)) {
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case I2C_SPEED_STANDARD:
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i2c_speed = 100000U; /* 100 KHz */
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break;
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case I2C_SPEED_FAST:
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i2c_speed = 400000U; /* 400 KHz */
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break;
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case I2C_SPEED_FAST_PLUS:
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case I2C_SPEED_HIGH:
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case I2C_SPEED_ULTRA:
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default:
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LOG_ERR("Unsupported I2C speed requested");
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return -ENOTSUP;
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}
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/* Calculate prescale value */
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prescale = (config->f_sys / (i2c_speed * 5U)) - 1;
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/* Configure peripheral with calculated prescale */
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sys_write8((uint8_t) (0xFF & prescale), I2C_REG(config, REG_PRESCALE_LOW));
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sys_write8((uint8_t) (0xFF & (prescale >> 8)),
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I2C_REG(config, REG_PRESCALE_HIGH));
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/* Support I2C Master mode only */
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if (!(dev_config & I2C_MODE_CONTROLLER)) {
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LOG_ERR("I2C only supports operation as master");
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return -ENOTSUP;
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}
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/*
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* Driver does not support 10-bit addressing. This can be added
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* in the future when needed.
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*/
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if (dev_config & I2C_ADDR_10_BITS) {
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LOG_ERR("I2C driver does not support 10-bit addresses");
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return -ENOTSUP;
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}
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/* Enable the I2C peripheral */
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sys_write8(SF_CONTROL_EN, I2C_REG(config, REG_CONTROL));
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return 0;
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}
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static int i2c_sifive_transfer(const struct device *dev,
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struct i2c_msg *msgs,
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uint8_t num_msgs,
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uint16_t addr)
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{
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int rc = 0;
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/* Check for NULL pointers */
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if (dev == NULL) {
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LOG_ERR("Device handle is NULL");
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return -EINVAL;
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}
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if (dev->config == NULL) {
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LOG_ERR("Device config is NULL");
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return -EINVAL;
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}
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if (msgs == NULL) {
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return -EINVAL;
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}
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for (int i = 0; i < num_msgs; i++) {
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if (msgs[i].flags & I2C_MSG_READ) {
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rc = i2c_sifive_read_msg(dev, &(msgs[i]), addr);
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} else {
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rc = i2c_sifive_write_msg(dev, &(msgs[i]), addr);
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}
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if (rc != 0) {
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LOG_ERR("I2C failed to transfer messages\n");
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return rc;
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}
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}
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return 0;
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};
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static int i2c_sifive_init(const struct device *dev)
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{
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const struct i2c_sifive_cfg *config = dev->config;
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uint32_t dev_config = 0U;
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int rc = 0;
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dev_config = (I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->f_bus));
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rc = i2c_sifive_configure(dev, dev_config);
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if (rc != 0) {
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LOG_ERR("Failed to configure I2C on init");
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return rc;
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}
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return 0;
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}
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static struct i2c_driver_api i2c_sifive_api = {
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.configure = i2c_sifive_configure,
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.transfer = i2c_sifive_transfer,
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};
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/* Device instantiation */
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#define I2C_SIFIVE_INIT(n) \
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static struct i2c_sifive_cfg i2c_sifive_cfg_##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.f_sys = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY, \
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.f_bus = DT_INST_PROP(n, clock_frequency), \
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}; \
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I2C_DEVICE_DT_INST_DEFINE(n, \
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i2c_sifive_init, \
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NULL, \
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NULL, \
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&i2c_sifive_cfg_##n, \
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POST_KERNEL, \
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CONFIG_I2C_INIT_PRIORITY, \
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&i2c_sifive_api);
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DT_INST_FOREACH_STATUS_OKAY(I2C_SIFIVE_INIT)
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