a7bda08960
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM code for Armv-8 Aarch32 is written for Arm mode only. This Soc has a general purpose register that can set the core TEINIT signal to change the mode exceptions are taken before booting up the core. The debugger startup scripts or firmware booting up the core may configure this bit to Thumb mode, as is the case of the NXP S32 debug probe startup scripts for S32ZE. Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value is ignored and exceptions are always taken into Arm mode, compatible with current Zephyr ASM code. At least until taking execeptions in Thumb mode is supported in Zephyr. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| CMakeLists.txt | ||
| Kconfig | ||